1
Fork 0
mirror of https://github.com/Steffo99/riscv-plus.git synced 2024-11-21 15:44:27 +00:00

Update README

This commit is contained in:
Steffo 2019-05-13 19:17:08 +02:00
parent db8cae6fad
commit 2e61883610

View file

@ -1,3 +1,5 @@
# RISC-V Assembly
Really basic RISC-V support.
Really basic RISC-V syntax highlighting for VSC.
Propose improvements and report bugs [on GitHub](https://github.com/Steffo99/riscv-plus/issues).