steffo/riscv-plus
steffo/riscv-plus
1
Fork 0
mirror of https://github.com/Steffo99/riscv-plus.git synced 2024-11-21 23:54:27 +00:00
Code Activity

Update README

Browse source
This commit is contained in:
Steffo 2019-05-13 19:17:08 +02:00
parent db8cae6fad
commit 2e61883610
1 changed files with 3 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
README.md
View file

@ -1,3 +1,5 @@
# RISC-V Assembly
Really basic RISC-V support.
Really basic RISC-V syntax highlighting for VSC.
Propose improvements and report bugs [on GitHub](https://github.com/Steffo99/riscv-plus/issues).