unimore/hpc-2022-g3
unimore/hpc-2022-g3
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Gianluca Brilli 2021-05-17 08:56:43 +02:00
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hls/lab2/README.md
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exercise 1: design solo PS e AXI Timer;
exercise 2: mmult baseline
exercise 3: mmult pipelined
exercise 4: mmult con BRAM
exercise 5: mmult Unrolled
exercise 6: mmult Array Part
exercise 7: mmult Pipeline outer
exercise 8: mmult Pipeline outer 200MHz
exercise 9: mmult Pipeline outer 300MHz
* exercise 1: design solo PS e AXI Timer
* exercise 2: mmult baseline
* exercise 3: mmult pipelined
* exercise 4: mmult con BRAM
* exercise 5: mmult Unrolled
* exercise 6: mmult Array Part
* exercise 7: mmult Pipeline outer
* exercise 8: mmult Pipeline outer 200MHz
* exercise 9: mmult Pipeline outer 300MHz