diff --git a/hls/lab2/sw/lscript.ld b/hls/lab2/sw/mmult_hw/lscript.ld similarity index 100% rename from hls/lab2/sw/lscript.ld rename to hls/lab2/sw/mmult_hw/lscript.ld diff --git a/hls/lab2/sw/mmult_hw/main.c b/hls/lab2/sw/mmult_hw/main.c new file mode 100644 index 0000000..e89f6e7 --- /dev/null +++ b/hls/lab2/sw/mmult_hw/main.c @@ -0,0 +1,57 @@ +#include +#include "platform.h" +#include "xil_printf.h" +#include "xparameters.h" +#include "xmmult.h" +#include "xil_cache.h" +#include "xtmrctr.h" + + +int main() +{ + init_platform(); + + XTmrCtr timer; + XTmrCtr_Initialize(&timer, XPAR_AXI_TIMER_0_DEVICE_ID); + + const int MAX_DIM = 64; + + int in1[MAX_DIM*MAX_DIM]; + int in2[MAX_DIM*MAX_DIM]; + int out[MAX_DIM*MAX_DIM]; + + for(int i = 0; i < MAX_DIM*MAX_DIM; i++) { + in1[i] = i; + in2[i] = i; + out[i] = 0; + } + + XTmrCtr_Start(&timer, 0); + Xil_DCacheFlush(); + + XMmult mmult; + XMmult_Initialize(&mmult, XPAR_MMULT_0_DEVICE_ID); + + XMmult_Set_in1(&mmult, (u32)in1); + XMmult_Set_in2(&mmult, (u32)in2); + XMmult_Set_out_r(&mmult, (u32)out); + XMmult_Set_dim(&mmult, MAX_DIM); + + XMmult_Start(&mmult); + + while(!XMmult_IsDone(&mmult)); + + Xil_DCacheInvalidate(); + + XTmrCtr_Stop(&timer, 0); + +// for(int i = 0; i < MAX_DIM*MAX_DIM; i++) { +// printf("%d\n", out[i]); +// } + + printf("clocks: %d\n", XTmrCtr_GetValue(&timer, 0)); + + cleanup_platform(); + + return 0; +} diff --git a/hls/lab2/sw/platform.c b/hls/lab2/sw/mmult_hw/platform.c similarity index 100% rename from hls/lab2/sw/platform.c rename to hls/lab2/sw/mmult_hw/platform.c diff --git a/hls/lab2/sw/platform.h b/hls/lab2/sw/mmult_hw/platform.h similarity index 100% rename from hls/lab2/sw/platform.h rename to hls/lab2/sw/mmult_hw/platform.h diff --git a/hls/lab2/sw/platform_config.h b/hls/lab2/sw/mmult_hw/platform_config.h similarity index 100% rename from hls/lab2/sw/platform_config.h rename to hls/lab2/sw/mmult_hw/platform_config.h diff --git a/hls/lab2/sw/mmult_sw/lscript.ld b/hls/lab2/sw/mmult_sw/lscript.ld new file mode 100644 index 0000000..6b49b6b --- /dev/null +++ b/hls/lab2/sw/mmult_sw/lscript.ld @@ -0,0 +1,322 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: 2020.1 */ +/* */ +/* Copyright (c) 2010-2019 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : ARM v8 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x8000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x8000; + +_EL0_STACK_SIZE = DEFINED(_EL0_STACK_SIZE) ? _EL0_STACK_SIZE : 1024; +_EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 2048; +_EL2_STACK_SIZE = DEFINED(_EL2_STACK_SIZE) ? _EL2_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + psu_ddr_0_MEM_0 : ORIGIN = 0x0, LENGTH = 0x7FF00000 + psu_ocm_ram_0_MEM_0 : ORIGIN = 0xFFFC0000, LENGTH = 0x40000 +} + +/* Specify the default entry point to the program */ + +ENTRY(_vector_table) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.text : { + KEEP (*(.vectors)) + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > psu_ddr_0_MEM_0 + +.init (ALIGN(64)) : { + KEEP (*(.init)) +} > psu_ddr_0_MEM_0 + +.fini (ALIGN(64)) : { + KEEP (*(.fini)) +} > psu_ddr_0_MEM_0 + +.interp : { + KEEP (*(.interp)) +} > psu_ddr_0_MEM_0 + +.note-ABI-tag : { + KEEP (*(.note-ABI-tag)) +} > psu_ddr_0_MEM_0 + +.rodata : { + . = ALIGN(64); + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > psu_ddr_0_MEM_0 + +.rodata1 : { + . = ALIGN(64); + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > psu_ddr_0_MEM_0 + +.sdata2 : { + . = ALIGN(64); + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > psu_ddr_0_MEM_0 + +.sbss2 : { + . = ALIGN(64); + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > psu_ddr_0_MEM_0 + +.data : { + . = ALIGN(64); + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > psu_ddr_0_MEM_0 + +.data1 : { + . = ALIGN(64); + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > psu_ddr_0_MEM_0 + +.got : { + *(.got) +} > psu_ddr_0_MEM_0 + +.got1 : { + *(.got1) +} > psu_ddr_0_MEM_0 + +.got2 : { + *(.got2) +} > psu_ddr_0_MEM_0 + +.note.gnu.build-id : { + KEEP (*(.note.gnu.build-id)) +} > psu_ddr_0_MEM_0 + +.ctors : { + . = ALIGN(64); + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.dtors : { + . = ALIGN(64); + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > psu_ddr_0_MEM_0 + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > psu_ddr_0_MEM_0 + +.eh_frame : { + *(.eh_frame) +} > psu_ddr_0_MEM_0 + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > psu_ddr_0_MEM_0 + +.gcc_except_table : { + *(.gcc_except_table) +} > psu_ddr_0_MEM_0 + +.mmu_tbl0 (ALIGN(4096)) : { + __mmu_tbl0_start = .; + *(.mmu_tbl0) + __mmu_tbl0_end = .; +} > psu_ddr_0_MEM_0 + +.mmu_tbl1 (ALIGN(4096)) : { + __mmu_tbl1_start = .; + *(.mmu_tbl1) + __mmu_tbl1_end = .; +} > psu_ddr_0_MEM_0 + +.mmu_tbl2 (ALIGN(4096)) : { + __mmu_tbl2_start = .; + *(.mmu_tbl2) + __mmu_tbl2_end = .; +} > psu_ddr_0_MEM_0 + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > psu_ddr_0_MEM_0 + +.preinit_array : { + . = ALIGN(64); + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > psu_ddr_0_MEM_0 + +.init_array : { + . = ALIGN(64); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > psu_ddr_0_MEM_0 + +.fini_array : { + . = ALIGN(64); + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > psu_ddr_0_MEM_0 + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > psu_ddr_0_MEM_0 + +.sdata : { + . = ALIGN(64); + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > psu_ddr_0_MEM_0 + +.sbss (NOLOAD) : { + . = ALIGN(64); + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + . = ALIGN(64); + __sbss_end = .; +} > psu_ddr_0_MEM_0 + +.tdata : { + . = ALIGN(64); + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > psu_ddr_0_MEM_0 + +.tbss : { + . = ALIGN(64); + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > psu_ddr_0_MEM_0 + +.bss (NOLOAD) : { + . = ALIGN(64); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(64); + __bss_end__ = .; +} > psu_ddr_0_MEM_0 + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(64); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > psu_ddr_0_MEM_0 + +.stack (NOLOAD) : { + . = ALIGN(64); + _el3_stack_end = .; + . += _STACK_SIZE; + __el3_stack = .; + _el2_stack_end = .; + . += _EL2_STACK_SIZE; + . = ALIGN(64); + __el2_stack = .; + _el1_stack_end = .; + . += _EL1_STACK_SIZE; + . = ALIGN(64); + __el1_stack = .; + _el0_stack_end = .; + . += _EL0_STACK_SIZE; + . = ALIGN(64); + __el0_stack = .; +} > psu_ddr_0_MEM_0 + +_end = .; +} + diff --git a/hls/lab2/sw/main.c b/hls/lab2/sw/mmult_sw/main.c similarity index 63% rename from hls/lab2/sw/main.c rename to hls/lab2/sw/mmult_sw/main.c index 3489a87..f4254ae 100644 --- a/hls/lab2/sw/main.c +++ b/hls/lab2/sw/mmult_sw/main.c @@ -2,33 +2,12 @@ #include "platform.h" #include "xil_printf.h" #include "xtmrctr.h" -#include "xmmult.h" #include "xparameters.h" #include "xil_cache.h" #include "xil_io.h" #define MAX_SIZE 64 -void mmult_hardware( - XMmult* mmult_accel, - u32 in1, // Input matrix 1 - u32 in2, // Input matrix 2 - u32 out, // Output matrix (out = A x B) - u32 dim // Size of one dimension of matrix - ) { - - XMmult_Set_in1(mmult_accel, in1); - XMmult_Set_in2(mmult_accel, in2); - XMmult_Set_out_r(mmult_accel, out); - XMmult_Set_dim(mmult_accel, MAX_SIZE); - - XMmult_Start(mmult_accel); - - while(!XMmult_IsDone(mmult_accel)){ - /* wait polling */ - } -} - void mmult_software( int* in1, // Input matrix 1 int* in2, // Input matrix 2 @@ -46,8 +25,6 @@ void mmult_software( } } - - int main() { init_platform(); @@ -67,29 +44,16 @@ int main() in2[i] = i; out[i] = 0; } - Xil_DCacheFlush(); XTmrCtr timer; XTmrCtr_Initialize(&timer, XPAR_AXI_TIMER_0_DEVICE_ID); - XMmult mmult_accel; - XMmult_Initialize(&mmult_accel, 0); - - XTmrCtr_Start(&timer, 0); - mmult_hardware(&mmult_accel, (u32)in1, (u32)in2, (u32)out, MAX_SIZE); - XTmrCtr_Stop(&timer, 0); - - printf("hardware: %d\n", XTmrCtr_GetValue(&timer, 0)); - - Xil_DCacheDisable(); - XTmrCtr_Start(&timer, 0); mmult_software(in1, in2, out, MAX_SIZE); XTmrCtr_Stop(&timer, 0); printf("software: %d\n", XTmrCtr_GetValue(&timer, 0)); - Xil_DCacheInvalidate(); // printf("out\n"); // for(int i = 0; i < MAX_SIZE*MAX_SIZE; i++) { // printf("%d \n", out[i]); diff --git a/hls/lab2/sw/mmult_sw/platform.c b/hls/lab2/sw/mmult_sw/platform.c new file mode 100644 index 0000000..0ee2dcb --- /dev/null +++ b/hls/lab2/sw/mmult_sw/platform.c @@ -0,0 +1,111 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xparameters.h" +#include "xil_cache.h" + +#include "platform_config.h" + +/* + * Uncomment one of the following two lines, depending on the target, + * if ps7/psu init source files are added in the source directory for + * compiling example outside of SDK. + */ +/*#include "ps7_init.h"*/ +/*#include "psu_init.h"*/ + +#ifdef STDOUT_IS_16550 + #include "xuartns550_l.h" + + #define UART_BAUD 9600 +#endif + +void +enable_caches() +{ +#ifdef __PPC__ + Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK); + Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK); +#elif __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheEnable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheEnable(); +#endif +#endif +} + +void +disable_caches() +{ +#ifdef __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheDisable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheDisable(); +#endif +#endif +} + +void +init_uart() +{ +#ifdef STDOUT_IS_16550 + XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); + XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); +#endif + /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */ +} + +void +init_platform() +{ + /* + * If you want to run this example outside of SDK, + * uncomment one of the following two lines and also #include "ps7_init.h" + * or #include "ps7_init.h" at the top, depending on the target. + * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included + * along with this example source files for compilation. + */ + /* ps7_init();*/ + /* psu_init();*/ + enable_caches(); + init_uart(); +} + +void +cleanup_platform() +{ + disable_caches(); +} diff --git a/hls/lab2/sw/mmult_sw/platform.h b/hls/lab2/sw/mmult_sw/platform.h new file mode 100644 index 0000000..e273e37 --- /dev/null +++ b/hls/lab2/sw/mmult_sw/platform.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef __PLATFORM_H_ +#define __PLATFORM_H_ + +#include "platform_config.h" + +void init_platform(); +void cleanup_platform(); + +#endif diff --git a/hls/lab2/sw/mmult_sw/platform_config.h b/hls/lab2/sw/mmult_sw/platform_config.h new file mode 100644 index 0000000..30d16a1 --- /dev/null +++ b/hls/lab2/sw/mmult_sw/platform_config.h @@ -0,0 +1,6 @@ +#ifndef __PLATFORM_CONFIG_H_ +#define __PLATFORM_CONFIG_H_ + +#define STDOUT_IS_PSU_UART +#define UART_DEVICE_ID 1 +#endif