This design is targeted for xczu3eg board (part number: xczu3eg-sbva484-1-e)

Zynq UltraScale+ Design Summary

Device	xczu3eg
SpeedGrade	-1
Part	xczu3eg-sbva484-1-e
Description	Zynq UltraScale+ PS Configuration Report
Vendor	Xilinx

MIO Table View

MIO Pin	Peripheral	Signal	IO Type	Speed	Pullup	Direction	Drive Strength(mA)
MIO 0	UART 1	txd	cmos	fast	pullup	out	12
MIO 1	UART 1	rxd	cmos	fast	pullup	in	12
MIO 2	UART 0	rxd	cmos	fast	pullup	in	12
MIO 3	UART 0	txd	cmos	fast	pullup	out	12
MIO 4	I2C 1	scl_out	cmos	fast	pullup	inout	12
MIO 5	I2C 1	sda_out	cmos	fast	pullup	inout	12
MIO 6	SPI 1	sclk_out	cmos	fast	pullup	inout	12
MIO 7	GPIO0 MIO	gpio0[7]	cmos	fast	pullup	inout	12
MIO 8	GPIO0 MIO	gpio0[8]	cmos	fast	pullup	inout	12
MIO 9	SPI 1	n_ss_out[0]	cmos	fast	pullup	inout	12
MIO 10	SPI 1	miso	cmos	fast	pullup	inout	12
MIO 11	SPI 1	mosi	cmos	fast	pullup	inout	12
MIO 12	GPIO0 MIO	gpio0[12]	cmos	fast	pullup	inout	12
MIO 13	SD 0	sdio0_data_out[0]	cmos	fast	pullup	inout	4
MIO 14	SD 0	sdio0_data_out[1]	cmos	fast	pullup	inout	4
MIO 15	SD 0	sdio0_data_out[2]	cmos	fast	pullup	inout	4
MIO 16	SD 0	sdio0_data_out[3]	cmos	fast	pullup	inout	4
MIO 17	GPIO0 MIO	gpio0[17]	cmos	fast	pullup	inout	12
MIO 18	GPIO0 MIO	gpio0[18]	cmos	fast	pullup	inout	12
MIO 19	GPIO0 MIO	gpio0[19]	cmos	fast	pullup	inout	12
MIO 20	GPIO0 MIO	gpio0[20]	cmos	fast	pullup	inout	12
MIO 21	SD 0	sdio0_cmd_out	cmos	fast	pullup	inout	4
MIO 22	SD 0	sdio0_clk_out	cmos	fast	pullup	out	4
MIO 23	GPIO0 MIO	gpio0[23]	cmos	fast	pullup	inout	12
MIO 24	SD 0	sdio0_cd_n	cmos	fast	pullup	in	12
MIO 25	GPIO0 MIO	gpio0[25]	cmos	fast	pullup	inout	12
MIO 26	PMU GPI 0	gpi[0]	cmos	fast	pullup	in	12
MIO 27	DPAUX	dp_aux_data_out	cmos	fast	pullup	out	12
MIO 28	DPAUX	dp_hot_plug_detect	cmos	fast	pullup	in	12
MIO 29	DPAUX	dp_aux_data_oe	cmos	fast	pullup	out	12
MIO 30	DPAUX	dp_aux_data_in	cmos	fast	pullup	in	12
MIO 31	GPIO1 MIO	gpio1[31]	cmos	fast	pullup	inout	12
MIO 32	PMU GPO 0	gpo[0]	cmos	fast	pullup	out	12
MIO 33	PMU GPO 1	gpo[1]	cmos	fast	pullup	out	12
MIO 34	PMU GPO 2	gpo[2]	cmos	fast	pullup	out	12
MIO 35	GPIO1 MIO	gpio1[35]	cmos	fast	pullup	inout	12
MIO 36	GPIO1 MIO	gpio1[36]	cmos	fast	pullup	inout	12
MIO 37	GPIO1 MIO	gpio1[37]	cmos	fast	pullup	inout	12
MIO 38	SPI 0	sclk_out	cmos	fast	pullup	inout	12
MIO 39	GPIO1 MIO	gpio1[39]	cmos	fast	pullup	inout	12
MIO 40	GPIO1 MIO	gpio1[40]	cmos	fast	pullup	inout	12
MIO 41	SPI 0	n_ss_out[0]	cmos	fast	pullup	inout	12
MIO 42	SPI 0	miso	cmos	fast	pullup	inout	12
MIO 43	SPI 0	mosi	cmos	fast	pullup	inout	12
MIO 44	GPIO1 MIO	gpio1[44]	cmos	fast	pullup	inout	12
MIO 45	GPIO1 MIO	gpio1[45]	cmos	fast	pullup	inout	12
MIO 46	SD 1	sdio1_data_out[0]	cmos	fast	pullup	inout	12
MIO 47	SD 1	sdio1_data_out[1]	cmos	fast	pullup	inout	12
MIO 48	SD 1	sdio1_data_out[2]	cmos	fast	pullup	inout	12
MIO 49	SD 1	sdio1_data_out[3]	cmos	fast	pullup	inout	12
MIO 50	SD 1	sdio1_cmd_out	cmos	fast	pullup	inout	12
MIO 51	SD 1	sdio1_clk_out	cmos	fast	pullup	out	12
MIO 52	USB 0	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 53	USB 0	ulpi_dir	cmos	fast	pullup	in	12
MIO 54	USB 0	ulpi_tx_data[2]	cmos	fast	pullup	inout	12
MIO 55	USB 0	ulpi_nxt	cmos	fast	pullup	in	12
MIO 56	USB 0	ulpi_tx_data[0]	cmos	fast	pullup	inout	12
MIO 57	USB 0	ulpi_tx_data[1]	cmos	fast	pullup	inout	12
MIO 58	USB 0	ulpi_stp	cmos	fast	pullup	out	12
MIO 59	USB 0	ulpi_tx_data[3]	cmos	fast	pullup	inout	12
MIO 60	USB 0	ulpi_tx_data[4]	cmos	fast	pullup	inout	12
MIO 61	USB 0	ulpi_tx_data[5]	cmos	fast	pullup	inout	12
MIO 62	USB 0	ulpi_tx_data[6]	cmos	fast	pullup	inout	12
MIO 63	USB 0	ulpi_tx_data[7]	cmos	fast	pullup	inout	12
MIO 64	USB 1	ulpi_clk_in	cmos	fast	pullup	in	12
MIO 65	USB 1	ulpi_dir	cmos	fast	pullup	in	12
MIO 66	USB 1	ulpi_tx_data[2]	cmos	fast	pullup	inout	12
MIO 67	USB 1	ulpi_nxt	cmos	fast	pullup	in	12
MIO 68	USB 1	ulpi_tx_data[0]	cmos	fast	pullup	inout	12
MIO 69	USB 1	ulpi_tx_data[1]	cmos	fast	pullup	inout	12
MIO 70	USB 1	ulpi_stp	cmos	fast	pullup	out	12
MIO 71	USB 1	ulpi_tx_data[3]	cmos	fast	pullup	inout	12
MIO 72	USB 1	ulpi_tx_data[4]	cmos	fast	pullup	inout	12
MIO 73	USB 1	ulpi_tx_data[5]	cmos	fast	pullup	inout	12
MIO 74	USB 1	ulpi_tx_data[6]	cmos	fast	pullup	inout	12
MIO 75	USB 1	ulpi_tx_data[7]	cmos	fast	pullup	inout	12
MIO 76	GPIO2 MIO	gpio2[76]	cmos	fast	pullup	inout	12
MIO 77	GPIO2 MIO	gpio2[77]	cmos	fast	pullup	inout	12

PS Clocks information

PSS REF CLK : 33.333

Name	Source	Input Frequency (MHz)
APLL	PSS_REF_CLK	2400.000
DPLL	PSS_REF_CLK	2133.333
VPLL	PSS_REF_CLK	2366.667
RPLL	PSS_REF_CLK	2333.333
IOPLL	PSS_REF_CLK	2333.333

Peripheral	Source	Actual Frequency (MHz)
USB0 freq (MHz)	IOPLL	250.000000
USB1 freq (MHz)	IOPLL	250.000000
SDIO0 freq (MHz)	IOPLL	187.500000
SDIO1 freq (MHz)	IOPLL	187.500000
UART0 freq (MHz)	IOPLL	100.000000
UART1 freq (MHz)	IOPLL	100.000000
I2C1 freq (MHz)	IOPLL	100.000000
SPI0 freq (MHz)	IOPLL	187.500000
SPI1 freq (MHz)	IOPLL	187.500000
CPU_R5 freq (MHz)	IOPLL	500.000000
IOU_SWITCH freq (MHz)	IOPLL	250.000000
LPD_SWITCH freq (MHz)	IOPLL	500.000000
LPD_LSBUS freq (MHz)	IOPLL	100.000000
TIMESTAMP freq (MHz)	IOPLL	100.000000
PSU__CRL_APB__USB3_REF_CTRL__freqmhz	IOPLL	20.000000
PCAP freq (MHz)	IOPLL	187.500000
DBG_LPD freq (MHz)	IOPLL	250.000000
ADMA freq (MHz)	IOPLL	500.000000
PL0 freq (MHz)	IOPLL	100.000000
AMS freq (MHz)	IOPLL	51.724136
ACPU freq (MHz)	APLL	1200.000000
DBG FPD freq (MHz)	IOPLL	250.000000
DP VIDEO freq (MHz)	VPLL	297.029572
DP AUDIO freq (MHz)	RPLL	24.576040
DP STC freq (MHz)	RPLL	26.214443
DDR_CTRL freq MHz)	DPLL	266.666656
GPU freq (MHz)	IOPLL	500.000000
GDMA freq (MHz)	APLL	600.000000
DPDMA freq (MHz)	APLL	600.000000
TOPSW_MAIN freq (MHz)	DPLL	533.333313
TOPSW_LSBUS freq (MHz)	IOPLL	100.000000
DBG TSTMP freq (MHz)	IOPLL	250.000000

DDR Memory information

Parameter name	Value	Description
ENABLE	1	Enable the PS DDR Controller
DDR Interface freq (MHz)	533	--
MEMORY TYPE	LPDDR 4	Type of memory interface
DM DBI	Components
BUS WIDTH	32 Bit	Data width of DDR interface, not including ECC data width
ECC	Disabled	Enables error correction code support
SPEED BIN	LPDDR4_1066	Speed Bin
CL	NA	Column Access Strobe (CAS) latency in memory clock cycles. It refers to the amount of time it takes for data to appear on the pins of the memory module
CWL	NA	CAS write latency setting in memory clock cycles
DDR AL	0	Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths
T RCD	10	tRCD. Row address to column address delay time. It is the time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS)
T RP	12	Precharge Time is the number of clock cycles needed to terminate access to an open row of memory and open access to the next row
T RC	63	Row cycle time (ns)
T RAS MIN	42	Minimum number of memory clock cycles required between an Active and Precharge command
T FAW	40.0	Determines the number of activates that can be performed within a certain window of time
DRAM WIDTH	32 Bits	Width of individual DRAM components
DEVICE CAPACITY	16384 MBits	Storage capacity of individual DRAM components
BG ADDR COUNT	NA	Number of bank group address pins
RANK ADDR COUNT	0	Dual-rank or dual-DIMM configuration of DRAM. Addressed using two chip-select bits (CS_N)
BANK ADDR COUNT	3	Number of bank address pins
ROW ADDR COUNT	16	Number of row address pins
COL ADDR COUNT	10	Number of column address bits
C_DDR_RAM_HIGHADDR	0x7FFFFFFF	--

GT lanes information

Protocol	GT lane#	Ref Clk Sel	Ref freq (MHz)
DP	GT Lane0	Ref Clk1	27
USB0	GT Lane2	Ref Clk0	26
USB1	GT Lane3	Ref Clk0	26