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19 lines
671 B
C++
19 lines
671 B
C++
#define TEST_DATA_SIZE 4194304 // 2^22
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const unsigned int c_dim = TEST_DATA_SIZE;
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void vadd(int *a, int *b, int *c, const int len)
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{
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//TODO: split bundles on three different AXI4 bus
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#pragma HLS INTERFACE m_axi port=a offset=slave bundle=mem
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#pragma HLS INTERFACE m_axi port=b offset=slave bundle=mem
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#pragma HLS INTERFACE m_axi port=c offset=slave bundle=mem
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#pragma HLS INTERFACE s_axilite port=len bundle=params
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#pragma HLS INTERFACE s_axilite port=return bundle=params
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loop: for(int i = 0; i < len; i++) {
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//TODO: insert pipeline directive
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#pragma HLS LOOP_TRIPCOUNT min=c_dim max=c_dim
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c[i] = a[i] + b[i];
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}
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}
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