unimore/hpc-2022-g3
unimore/hpc-2022-g3
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hpc-2022-g3/hls/lab2
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Gianluca Brilli 7cbe5bad64 readme modified
2021-05-17 08:56:43 +02:00
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exported_ips solutions for HLS lab2 2021-05-17 08:53:47 +02:00
hw solutions for HLS lab2 2021-05-17 08:53:47 +02:00
sw solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_1.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_2.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_3.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_4.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_5.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_6.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_7.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_8.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
exercise_9.tcl solutions for HLS lab2 2021-05-17 08:53:47 +02:00
README.md readme modified 2021-05-17 08:56:43 +02:00

README.md

  • exercise 1: design solo PS e AXI Timer
  • exercise 2: mmult baseline
  • exercise 3: mmult pipelined
  • exercise 4: mmult con BRAM
  • exercise 5: mmult Unrolled
  • exercise 6: mmult Array Part
  • exercise 7: mmult Pipeline outer
  • exercise 8: mmult Pipeline outer 200MHz
  • exercise 9: mmult Pipeline outer 300MHz