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exported_ips | ||
hw | ||
sw | ||
exercise_1.tcl | ||
exercise_2.tcl | ||
exercise_3.tcl | ||
exercise_4.tcl | ||
exercise_5.tcl | ||
exercise_6.tcl | ||
exercise_7.tcl | ||
exercise_8.tcl | ||
exercise_9.tcl | ||
README.md |
exercise 1: design solo PS e AXI Timer; exercise 2: mmult baseline exercise 3: mmult pipelined exercise 4: mmult con BRAM exercise 5: mmult Unrolled exercise 6: mmult Array Part exercise 7: mmult Pipeline outer exercise 8: mmult Pipeline outer 200MHz exercise 9: mmult Pipeline outer 300MHz