drm/radeon/kms/DCE6.1: ss is not supported on the internal pplls
It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -474,7 +474,7 @@ static void atombios_crtc_program_ss(struct radeon_device *rdev,
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return;
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}
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args.v3.ucEnable = enable;
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if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
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if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
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args.v3.ucEnable = ATOM_DISABLE;
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} else if (ASIC_IS_DCE4(rdev)) {
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args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
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