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x86: c1e_idle: don't mark TSC unstable if CPU has invariant TSC

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Impact: Functional TSC is marked unstable on AMD family 0x10 and 0x11 CPUs.

This would be wrong because for those CPUs "invariant TSC" means:

   "The TSC counts at the same rate in all P-states, all C states, S0,
   or S1"

(See "Processor BIOS and Kernel Developer's Guides" for those CPUs.)

[ tglx: Changed C1E to AMD C1E in the printks to avoid confusion 
	with Intel C1E ]

Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Andreas Herrmann 2008-09-18 21:12:10 +02:00 committed by Thomas Gleixner
parent a8d6829044
commit 09bfeea13c
1 changed files with 3 additions and 2 deletions
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5
arch/x86/kernel/process.c
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@ -270,8 +270,9 @@ static void c1e_idle(void)
rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
if (lo & K8_INTP_C1E_ACTIVE_MASK) {
c1e_detected = 1;
mark_tsc_unstable("TSC halt in C1E");
printk(KERN_INFO "System has C1E enabled\n");
if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
mark_tsc_unstable("TSC halt in AMD C1E");
printk(KERN_INFO "System has AMD C1E enabled\n");
set_cpu_cap(&boot_cpu_data, X86_FEATURE_AMDC1E);
}
}