RISC-V Fixes for 6.0-rc5

* A pair of device tree fixes for the Polarfire SOC.
 * A fix to avoid overflowing the PMU counter array when firmware
   incorrectly reports the number of supported counters, which manifests
   on OpenSBI versions prior to 1.1.
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Merge tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

Pull RISC-V fixes from Palmer Dabbelt:

 - A pair of device tree fixes for the Polarfire SOC

 - A fix to avoid overflowing the PMU counter array when firmware
   incorrectly reports the number of supported counters, which manifests
   on OpenSBI versions prior to 1.1

* tag 'riscv-for-linus-6.0-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  perf: RISC-V: fix access beyond allocated array
  riscv: dts: microchip: use an mpfs specific l2 compatible
  dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible

Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

@@ -17,9 +17,6 @@ description:
   acts as directory-based coherency manager.
   All the properties in ePAPR/DeviceTree specification applies for this platform.
 
-allOf:
-  - $ref: /schemas/cache-controller.yaml#
-
 select:
   properties:
     compatible:
@@ -33,11 +30,16 @@ select:
 
 properties:
   compatible:
-    items:
+    oneOf:
+      - items:
           - enum:
               - sifive,fu540-c000-ccache
               - sifive,fu740-c000-ccache
           - const: cache
+      - items:
+          - const: microchip,mpfs-ccache
+          - const: sifive,fu540-c000-ccache
+          - const: cache
 
   cache-block-size:
     const: 64
@@ -72,30 +74,47 @@ properties:
       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
 
-if:
+allOf:
+  - $ref: /schemas/cache-controller.yaml#
+
+  - if:
       properties:
         compatible:
           contains:
-        const: sifive,fu540-c000-ccache
+            enum:
+              - sifive,fu740-c000-ccache
+              - microchip,mpfs-ccache
 
-then:
-  properties:
-    interrupts:
-      description: |
-        Must contain entries for DirError, DataError and DataFail signals.
-      maxItems: 3
-    cache-sets:
-      const: 1024
-
-else:
+    then:
       properties:
         interrupts:
           description: |
             Must contain entries for DirError, DataError, DataFail, DirFail signals.
           minItems: 4
+
+    else:
+      properties:
+        interrupts:
+          description: |
+            Must contain entries for DirError, DataError and DataFail signals.
+          maxItems: 3
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: sifive,fu740-c000-ccache
+
+    then:
+      properties:
         cache-sets:
           const: 2048
 
+    else:
+      properties:
+        cache-sets:
+          const: 1024
+
 additionalProperties: false
 
 required:

arch/riscv/boot/dts/microchip/mpfs.dtsi

@@ -185,7 +185,7 @@ soc {
 		ranges;
 
 		cctrllr: cache-controller@2010000 {
-			compatible = "sifive,fu540-c000-ccache", "cache";
+			compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache";
 			reg = <0x0 0x2010000 0x0 0x1000>;
 			cache-block-size = <64>;
 			cache-level = <2>;

drivers/perf/riscv_pmu_sbi.c

@@ -473,7 +473,7 @@ static int pmu_sbi_get_ctrinfo(int nctr)
 	if (!pmu_ctr_list)
 		return -ENOMEM;
 
-	for (i = 0; i <= nctr; i++) {
+	for (i = 0; i < nctr; i++) {
 		ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0);
 		if (ret.error)
 			/* The logical counter ids are not expected to be contiguous */