dmaengine: imx-dma: remove dma_mode member of internal structure.
dmaengine now provides 'enum dma_transfer_direction' to properly specify DMA transfer direction. For this reason, DMA_MODE_* defines are replaced by this new type and therefore dma_mode member becomes redundant. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Javier Martin
Vinod Koul
parent
232e3c2c79
commit
2efc3449d7
1 changed files with 45 additions and 58 deletions
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@ -36,10 +36,6 @@
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#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
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#define IMX_DMA_CHANNELS 16
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#define DMA_MODE_READ 0
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#define DMA_MODE_WRITE 1
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#define DMA_MODE_MASK 1
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#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
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#define IMX_DMA_MEMSIZE_32 (0 << 4)
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#define IMX_DMA_MEMSIZE_8 (1 << 4)
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@ -133,7 +129,6 @@ enum imxdma_prep_type {
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*/
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struct imxdma_channel_internal {
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unsigned int dma_mode;
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struct scatterlist *sg;
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unsigned int resbytes;
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@ -154,7 +149,7 @@ struct imxdma_desc {
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dma_addr_t src;
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dma_addr_t dest;
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size_t len;
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unsigned int dmamode;
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enum dma_transfer_direction direction;
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enum imxdma_prep_type type;
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/* For memcpy and interleaved */
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unsigned int config_port;
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@ -239,8 +234,9 @@ static int imxdma_hw_chain(struct imxdma_channel_internal *imxdma)
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/*
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* imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
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*/
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static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterlist *sg)
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static inline int imxdma_sg_next(struct imxdma_desc *d, struct scatterlist *sg)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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struct imxdma_channel_internal *imxdma = &imxdmac->internal;
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unsigned long now;
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@ -248,7 +244,7 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
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if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
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imxdma->resbytes -= now;
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if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
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if (d->direction == DMA_DEV_TO_MEM)
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imx_dmav1_writel(sg->dma_address, DMA_DAR(imxdmac->channel));
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else
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imx_dmav1_writel(sg->dma_address, DMA_SAR(imxdmac->channel));
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@ -265,14 +261,12 @@ static inline int imxdma_sg_next(struct imxdma_channel *imxdmac, struct scatterl
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}
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static int
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imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
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unsigned int dma_length, unsigned int dev_addr,
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unsigned int dmamode)
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imxdma_setup_mem2mem_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
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unsigned int dma_length, unsigned int dev_addr)
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{
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int channel = imxdmac->channel;
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imxdmac->internal.sg = NULL;
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imxdmac->internal.dma_mode = dmamode;
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if (!dma_address) {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
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@ -286,38 +280,24 @@ imxdma_setup_single_hw(struct imxdma_channel *imxdmac, dma_addr_t dma_address,
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return -EINVAL;
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}
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if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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"dev_addr=0x%08x for read\n",
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channel, __func__, (unsigned int)dma_address,
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dma_length, dev_addr);
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pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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"dev_addr=0x%08x for write\n",
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channel, __func__, (unsigned int)dma_address,
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dma_length, dev_addr);
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imx_dmav1_writel(dev_addr, DMA_SAR(channel));
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imx_dmav1_writel(dma_address, DMA_DAR(channel));
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imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
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} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
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"dev_addr=0x%08x for write\n",
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channel, __func__, (unsigned int)dma_address,
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dma_length, dev_addr);
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imx_dmav1_writel(dma_address, DMA_SAR(channel));
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imx_dmav1_writel(dev_addr, DMA_DAR(channel));
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imx_dmav1_writel(imxdmac->internal.ccr_to_device,
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DMA_CCR(channel));
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} else {
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printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
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channel);
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return -EINVAL;
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}
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imx_dmav1_writel(dma_address, DMA_SAR(channel));
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imx_dmav1_writel(dev_addr, DMA_DAR(channel));
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imx_dmav1_writel(imxdmac->internal.ccr_to_device,
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DMA_CCR(channel));
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imx_dmav1_writel(dma_length, DMA_CNTR(channel));
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return 0;
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}
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static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
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static void imxdma_enable_hw(struct imxdma_desc *d)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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int channel = imxdmac->channel;
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unsigned long flags;
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@ -338,7 +318,7 @@ static void imxdma_enable_hw(struct imxdma_channel *imxdmac)
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imxdmac->internal.sg = sg_next(imxdmac->internal.sg);
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if (imxdmac->internal.sg) {
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u32 tmp;
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imxdma_sg_next(imxdmac, imxdmac->internal.sg);
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imxdma_sg_next(d, imxdmac->internal.sg);
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tmp = imx_dmav1_readl(DMA_CCR(channel));
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imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
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DMA_CCR(channel));
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@ -395,18 +375,18 @@ imxdma_config_channel_hw(struct imxdma_channel *imxdmac, unsigned int config_por
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}
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static int
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imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
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imxdma_setup_sg_hw(struct imxdma_desc *d,
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struct scatterlist *sg, unsigned int sgcount,
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unsigned int dma_length, unsigned int dev_addr,
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unsigned int dmamode)
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enum dma_transfer_direction direction)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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int channel = imxdmac->channel;
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if (imxdmac->internal.in_use)
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return -EBUSY;
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imxdmac->internal.sg = sg;
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imxdmac->internal.dma_mode = dmamode;
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imxdmac->internal.resbytes = dma_length;
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if (!sg || !sgcount) {
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@ -421,14 +401,14 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
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return -EINVAL;
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}
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if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
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if (direction == DMA_DEV_TO_MEM) {
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pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
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"dev_addr=0x%08x for read\n",
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channel, __func__, sg, sgcount, dma_length, dev_addr);
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imx_dmav1_writel(dev_addr, DMA_SAR(channel));
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imx_dmav1_writel(imxdmac->internal.ccr_from_device, DMA_CCR(channel));
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} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
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} else if (direction == DMA_MEM_TO_DEV) {
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pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
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"dev_addr=0x%08x for write\n",
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channel, __func__, sg, sgcount, dma_length, dev_addr);
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@ -441,7 +421,7 @@ imxdma_setup_sg_hw(struct imxdma_channel *imxdmac,
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return -EINVAL;
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}
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imxdma_sg_next(imxdmac, sg);
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imxdma_sg_next(d, sg);
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return 0;
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}
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@ -519,13 +499,26 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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{
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struct imxdma_channel_internal *imxdma = &imxdmac->internal;
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int chno = imxdmac->channel;
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struct imxdma_desc *desc;
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if (imxdma->sg) {
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u32 tmp;
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imxdma->sg = sg_next(imxdma->sg);
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if (imxdma->sg) {
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imxdma_sg_next(imxdmac, imxdma->sg);
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spin_lock(&imxdmac->lock);
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if (list_empty(&imxdmac->ld_active)) {
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spin_unlock(&imxdmac->lock);
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goto out;
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}
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desc = list_first_entry(&imxdmac->ld_active,
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struct imxdma_desc,
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node);
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spin_unlock(&imxdmac->lock);
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imxdma_sg_next(desc, imxdma->sg);
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tmp = imx_dmav1_readl(DMA_CCR(chno));
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@ -558,6 +551,7 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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}
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}
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out:
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imx_dmav1_writel(0, DMA_CCR(chno));
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imxdma->in_use = 0;
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/* Tasklet irq */
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@ -601,8 +595,7 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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d->config_port, d->config_mem, 0, 0);
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if (ret < 0)
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return ret;
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ret = imxdma_setup_single_hw(imxdmac, d->src,
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d->len, d->dest, d->dmamode);
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ret = imxdma_setup_mem2mem_hw(imxdmac, d->src, d->len, d->dest);
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if (ret < 0)
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return ret;
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break;
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@ -610,19 +603,15 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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/* Cyclic transfer is the same as slave_sg with special sg configuration. */
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case IMXDMA_DESC_CYCLIC:
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case IMXDMA_DESC_SLAVE_SG:
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if (d->dmamode == DMA_MODE_READ)
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ret = imxdma_setup_sg_hw(imxdmac, d->sg,
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d->sgcount, d->len, d->src, d->dmamode);
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else
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ret = imxdma_setup_sg_hw(imxdmac, d->sg,
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d->sgcount, d->len, d->dest, d->dmamode);
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ret = imxdma_setup_sg_hw(d, d->sg, d->sgcount, d->len,
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imxdmac->per_address, d->direction);
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if (ret < 0)
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return ret;
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break;
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default:
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return -EINVAL;
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}
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imxdma_enable_hw(imxdmac);
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imxdma_enable_hw(d);
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return 0;
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}
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@ -839,11 +828,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
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desc->sg = sgl;
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desc->sgcount = sg_len;
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desc->len = dma_length;
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desc->direction = direction;
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if (direction == DMA_DEV_TO_MEM) {
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desc->dmamode = DMA_MODE_READ;
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desc->src = imxdmac->per_address;
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} else {
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desc->dmamode = DMA_MODE_WRITE;
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desc->dest = imxdmac->per_address;
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}
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desc->desc.callback = NULL;
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@ -900,11 +888,10 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
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desc->sg = imxdmac->sg_list;
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desc->sgcount = periods;
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desc->len = IMX_DMA_LENGTH_LOOP;
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desc->direction = direction;
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if (direction == DMA_DEV_TO_MEM) {
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desc->dmamode = DMA_MODE_READ;
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desc->src = imxdmac->per_address;
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} else {
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desc->dmamode = DMA_MODE_WRITE;
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desc->dest = imxdmac->per_address;
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}
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desc->desc.callback = NULL;
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@ -934,7 +921,7 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
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desc->src = src;
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desc->dest = dest;
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desc->len = len;
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desc->dmamode = DMA_MODE_WRITE;
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desc->direction = DMA_MEM_TO_MEM;
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desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
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desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
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desc->desc.callback = NULL;
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