Staging: comedi: add rtd520 driver
This adds the rtd520 comedi driver to the build. From: Dan Christian <dac@ptolemy.arc.nasa.gov> Cc: David Schleef <ds@schleef.org> Cc: Frank Mori Hess <fmhess@users.sourceforge.net> Cc: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Dan Christian
Greg Kroah-Hartman
parent
11e865c1da
commit
3d9f073994
4 changed files with 3125 additions and 0 deletions
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@ -11,6 +11,7 @@ obj-$(CONFIG_COMEDI) += comedi_parport.o
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += mite.o
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += icp_multi.o
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += me4000.o
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += rtd520.o
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obj-$(CONFIG_COMEDI_PCI_DRIVERS) += s626.o
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# Comedi USB drivers
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429
drivers/staging/comedi/drivers/plx9080.h
Normal file
429
drivers/staging/comedi/drivers/plx9080.h
Normal file
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@ -0,0 +1,429 @@
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/* plx9080.h
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*
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* Copyright (C) 2002,2003 Frank Mori Hess <fmhess@users.sourceforge.net>
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*
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* I modified this file from the plx9060.h header for the
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* wanXL device driver in the linux kernel,
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* for the register offsets and bit definitions. Made minor modifications,
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* added plx9080 registers and
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* stripped out stuff that was specifically for the wanXL driver.
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* Note: I've only made sure the definitions are correct as far
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* as I make use of them. There are still various plx9060-isms
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* left in this header file.
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*
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********************************************************************
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*
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* Copyright (C) 1999 RG Studio s.c., http://www.rgstudio.com.pl/
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* Written by Krzysztof Halasa <khc@rgstudio.com.pl>
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*
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* Portions (C) SBE Inc., used by permission.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __COMEDI_PLX9080_H
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#define __COMEDI_PLX9080_H
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// descriptor block used for chained dma transfers
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struct plx_dma_desc {
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volatile uint32_t pci_start_addr;
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volatile uint32_t local_start_addr;
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/* transfer_size is in bytes, only first 23 bits of register are used */
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volatile uint32_t transfer_size;
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/* address of next descriptor (quad word aligned), plus some
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* additional bits (see PLX_DMA0_DESCRIPTOR_REG) */
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volatile uint32_t next;
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};
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/**********************************************************************
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** Register Offsets and Bit Definitions
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**
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** Note: All offsets zero relative. IE. Some standard base address
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** must be added to the Register Number to properly access the register.
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**
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**********************************************************************/
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#define PLX_LAS0RNG_REG 0x0000 /* L, Local Addr Space 0 Range Register */
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#define PLX_LAS1RNG_REG 0x00f0 /* L, Local Addr Space 1 Range Register */
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#define LRNG_IO 0x00000001 /* Map to: 1=I/O, 0=Mem */
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#define LRNG_ANY32 0x00000000 /* Locate anywhere in 32 bit */
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#define LRNG_LT1MB 0x00000002 /* Locate in 1st meg */
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#define LRNG_ANY64 0x00000004 /* Locate anywhere in 64 bit */
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#define LRNG_MEM_MASK 0xfffffff0 // bits that specify range for memory io
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#define LRNG_IO_MASK 0xfffffffa // bits that specify range for normal io
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#define PLX_LAS0MAP_REG 0x0004 /* L, Local Addr Space 0 Remap Register */
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#define PLX_LAS1MAP_REG 0x00f4 /* L, Local Addr Space 1 Remap Register */
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#define LMAP_EN 0x00000001 /* Enable slave decode */
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#define LMAP_MEM_MASK 0xfffffff0 // bits that specify decode for memory io
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#define LMAP_IO_MASK 0xfffffffa // bits that specify decode bits for normal io
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/* Mode/Arbitration Register.
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*/
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#define PLX_MARB_REG 0x8 /* L, Local Arbitration Register */
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#define PLX_DMAARB_REG 0xac
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enum marb_bits {
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MARB_LLT_MASK = 0x000000ff, /* Local Bus Latency Timer */
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MARB_LPT_MASK = 0x0000ff00, /* Local Bus Pause Timer */
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MARB_LTEN = 0x00010000, /* Latency Timer Enable */
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MARB_LPEN = 0x00020000, /* Pause Timer Enable */
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MARB_BREQ = 0x00040000, /* Local Bus BREQ Enable */
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MARB_DMA_PRIORITY_MASK = 0x00180000,
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MARB_LBDS_GIVE_UP_BUS_MODE = 0x00200000, /* local bus direct slave give up bus mode */
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MARB_DS_LLOCK_ENABLE = 0x00400000, /* direct slave LLOCKo# enable */
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MARB_PCI_REQUEST_MODE = 0x00800000,
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MARB_PCIv21_MODE = 0x01000000, /* pci specification v2.1 mode */
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MARB_PCI_READ_NO_WRITE_MODE = 0x02000000,
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MARB_PCI_READ_WITH_WRITE_FLUSH_MODE = 0x04000000,
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MARB_GATE_TIMER_WITH_BREQ = 0x08000000, /* gate local bus latency timer with BREQ */
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MARB_PCI_READ_NO_FLUSH_MODE = 0x10000000,
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MARB_USE_SUBSYSTEM_IDS = 0x20000000,
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};
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#define PLX_BIGEND_REG 0xc
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enum bigend_bits {
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BIGEND_CONFIG = 0x1, /* use big endian ordering for configuration register accesses */
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BIGEND_DIRECT_MASTER = 0x2,
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BIGEND_DIRECT_SLAVE_LOCAL0 = 0x4,
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BIGEND_ROM = 0x8,
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BIGEND_BYTE_LANE = 0x10, /* use byte lane consisting of most significant bits instead of least significant */
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BIGEND_DIRECT_SLAVE_LOCAL1 = 0x20,
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BIGEND_DMA1 = 0x40,
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BIGEND_DMA0 = 0x80,
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};
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/* Note: The Expansion ROM stuff is only relevant to the PC environment.
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** This expansion ROM code is executed by the host CPU at boot time.
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** For this reason no bit definitions are provided here.
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*/
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#define PLX_ROMRNG_REG 0x0010 /* L, Expn ROM Space Range Register */
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#define PLX_ROMMAP_REG 0x0014 /* L, Local Addr Space Range Register */
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#define PLX_REGION0_REG 0x0018 /* L, Local Bus Region 0 Descriptor */
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#define RGN_WIDTH 0x00000002 /* Local bus width bits */
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#define RGN_8BITS 0x00000000 /* 08 bit Local Bus */
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#define RGN_16BITS 0x00000001 /* 16 bit Local Bus */
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#define RGN_32BITS 0x00000002 /* 32 bit Local Bus */
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#define RGN_MWS 0x0000003C /* Memory Access Wait States */
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#define RGN_0MWS 0x00000000
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#define RGN_1MWS 0x00000004
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#define RGN_2MWS 0x00000008
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#define RGN_3MWS 0x0000000C
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#define RGN_4MWS 0x00000010
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#define RGN_6MWS 0x00000018
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#define RGN_8MWS 0x00000020
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#define RGN_MRE 0x00000040 /* Memory Space Ready Input Enable */
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#define RGN_MBE 0x00000080 /* Memory Space Bterm Input Enable */
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#define RGN_READ_PREFETCH_DISABLE 0x00000100
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#define RGN_ROM_PREFETCH_DISABLE 0x00000200
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#define RGN_READ_PREFETCH_COUNT_ENABLE 0x00000400
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#define RGN_RWS 0x003C0000 /* Expn ROM Wait States */
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#define RGN_RRE 0x00400000 /* ROM Space Ready Input Enable */
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#define RGN_RBE 0x00800000 /* ROM Space Bterm Input Enable */
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#define RGN_MBEN 0x01000000 /* Memory Space Burst Enable */
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#define RGN_RBEN 0x04000000 /* ROM Space Burst Enable */
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#define RGN_THROT 0x08000000 /* De-assert TRDY when FIFO full */
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#define RGN_TRD 0xF0000000 /* Target Ready Delay /8 */
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#define PLX_REGION1_REG 0x00f8 /* L, Local Bus Region 1 Descriptor */
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#define PLX_DMRNG_REG 0x001C /* L, Direct Master Range Register */
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#define PLX_LBAPMEM_REG 0x0020 /* L, Lcl Base Addr for PCI mem space */
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#define PLX_LBAPIO_REG 0x0024 /* L, Lcl Base Addr for PCI I/O space */
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#define PLX_DMMAP_REG 0x0028 /* L, Direct Master Remap Register */
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#define DMM_MAE 0x00000001 /* Direct Mstr Memory Acc Enable */
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#define DMM_IAE 0x00000002 /* Direct Mstr I/O Acc Enable */
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#define DMM_LCK 0x00000004 /* LOCK Input Enable */
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#define DMM_PF4 0x00000008 /* Prefetch 4 Mode Enable */
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#define DMM_THROT 0x00000010 /* Assert IRDY when read FIFO full */
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#define DMM_PAF0 0x00000000 /* Programmable Almost fill level */
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#define DMM_PAF1 0x00000020 /* Programmable Almost fill level */
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#define DMM_PAF2 0x00000040 /* Programmable Almost fill level */
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#define DMM_PAF3 0x00000060 /* Programmable Almost fill level */
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#define DMM_PAF4 0x00000080 /* Programmable Almost fill level */
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#define DMM_PAF5 0x000000A0 /* Programmable Almost fill level */
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#define DMM_PAF6 0x000000C0 /* Programmable Almost fill level */
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#define DMM_PAF7 0x000000D0 /* Programmable Almost fill level */
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#define DMM_MAP 0xFFFF0000 /* Remap Address Bits */
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#define PLX_CAR_REG 0x002C /* L, Configuration Address Register */
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#define CAR_CT0 0x00000000 /* Config Type 0 */
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#define CAR_CT1 0x00000001 /* Config Type 1 */
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#define CAR_REG 0x000000FC /* Register Number Bits */
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#define CAR_FUN 0x00000700 /* Function Number Bits */
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#define CAR_DEV 0x0000F800 /* Device Number Bits */
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#define CAR_BUS 0x00FF0000 /* Bus Number Bits */
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#define CAR_CFG 0x80000000 /* Config Spc Access Enable */
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#define PLX_DBR_IN_REG 0x0060 /* L, PCI to Local Doorbell Register */
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#define PLX_DBR_OUT_REG 0x0064 /* L, Local to PCI Doorbell Register */
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#define PLX_INTRCS_REG 0x0068 /* L, Interrupt Control/Status Reg */
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#define ICS_AERR 0x00000001 /* Assert LSERR on ABORT */
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#define ICS_PERR 0x00000002 /* Assert LSERR on Parity Error */
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#define ICS_SERR 0x00000004 /* Generate PCI SERR# */
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#define ICS_MBIE 0x00000008 // mailbox interrupt enable
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#define ICS_PIE 0x00000100 /* PCI Interrupt Enable */
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#define ICS_PDIE 0x00000200 /* PCI Doorbell Interrupt Enable */
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#define ICS_PAIE 0x00000400 /* PCI Abort Interrupt Enable */
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#define ICS_PLIE 0x00000800 /* PCI Local Int Enable */
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#define ICS_RAE 0x00001000 /* Retry Abort Enable */
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#define ICS_PDIA 0x00002000 /* PCI Doorbell Interrupt Active */
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#define ICS_PAIA 0x00004000 /* PCI Abort Interrupt Active */
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#define ICS_LIA 0x00008000 /* Local Interrupt Active */
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#define ICS_LIE 0x00010000 /* Local Interrupt Enable */
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#define ICS_LDIE 0x00020000 /* Local Doorbell Int Enable */
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#define ICS_DMA0_E 0x00040000 /* DMA #0 Interrupt Enable */
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#define ICS_DMA1_E 0x00080000 /* DMA #1 Interrupt Enable */
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#define ICS_LDIA 0x00100000 /* Local Doorbell Int Active */
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#define ICS_DMA0_A 0x00200000 /* DMA #0 Interrupt Active */
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#define ICS_DMA1_A 0x00400000 /* DMA #1 Interrupt Active */
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#define ICS_BIA 0x00800000 /* BIST Interrupt Active */
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#define ICS_TA_DM 0x01000000 /* Target Abort - Direct Master */
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#define ICS_TA_DMA0 0x02000000 /* Target Abort - DMA #0 */
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#define ICS_TA_DMA1 0x04000000 /* Target Abort - DMA #1 */
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#define ICS_TA_RA 0x08000000 /* Target Abort - Retry Timeout */
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#define ICS_MBIA(x) (0x10000000 << ((x) & 0x3)) // mailbox x is active
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#define PLX_CONTROL_REG 0x006C /* L, EEPROM Cntl & PCI Cmd Codes */
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#define CTL_RDMA 0x0000000E /* DMA Read Command */
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#define CTL_WDMA 0x00000070 /* DMA Write Command */
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#define CTL_RMEM 0x00000600 /* Memory Read Command */
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#define CTL_WMEM 0x00007000 /* Memory Write Command */
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#define CTL_USERO 0x00010000 /* USERO output pin control bit */
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#define CTL_USERI 0x00020000 /* USERI input pin bit */
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#define CTL_EE_CLK 0x01000000 /* EEPROM Clock line */
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#define CTL_EE_CS 0x02000000 /* EEPROM Chip Select */
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#define CTL_EE_W 0x04000000 /* EEPROM Write bit */
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#define CTL_EE_R 0x08000000 /* EEPROM Read bit */
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#define CTL_EECHK 0x10000000 /* EEPROM Present bit */
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#define CTL_EERLD 0x20000000 /* EEPROM Reload Register */
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#define CTL_RESET 0x40000000 /* !! Adapter Reset !! */
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#define CTL_READY 0x80000000 /* Local Init Done */
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#define PLX_ID_REG 0x70 // hard-coded plx vendor and device ids
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#define PLX_REVISION_REG 0x74 // silicon revision
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#define PLX_DMA0_MODE_REG 0x80 // dma channel 0 mode register
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#define PLX_DMA1_MODE_REG 0x94 // dma channel 0 mode register
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#define PLX_LOCAL_BUS_16_WIDE_BITS 0x1
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#define PLX_LOCAL_BUS_32_WIDE_BITS 0x3
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#define PLX_LOCAL_BUS_WIDTH_MASK 0x3
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#define PLX_DMA_EN_READYIN_BIT 0x40 // enable ready in input
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#define PLX_EN_BTERM_BIT 0x80 // enable BTERM# input
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#define PLX_DMA_LOCAL_BURST_EN_BIT 0x100 // enable local burst mode
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#define PLX_EN_CHAIN_BIT 0x200 // enables chaining
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#define PLX_EN_DMA_DONE_INTR_BIT 0x400 // enables interrupt on dma done
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#define PLX_LOCAL_ADDR_CONST_BIT 0x800 // hold local address constant (don't increment)
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#define PLX_DEMAND_MODE_BIT 0x1000 // enables demand-mode for dma transfer
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#define PLX_EOT_ENABLE_BIT 0x4000
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#define PLX_STOP_MODE_BIT 0x8000
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#define PLX_DMA_INTR_PCI_BIT 0x20000 // routes dma interrupt to pci bus (instead of local bus)
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#define PLX_DMA0_PCI_ADDRESS_REG 0x84 // pci address that dma transfers start at
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#define PLX_DMA1_PCI_ADDRESS_REG 0x98
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#define PLX_DMA0_LOCAL_ADDRESS_REG 0x88 // local address that dma transfers start at
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#define PLX_DMA1_LOCAL_ADDRESS_REG 0x9c
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#define PLX_DMA0_TRANSFER_SIZE_REG 0x8c // number of bytes to transfer (first 23 bits)
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#define PLX_DMA1_TRANSFER_SIZE_REG 0xa0
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#define PLX_DMA0_DESCRIPTOR_REG 0x90 // descriptor pointer register
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#define PLX_DMA1_DESCRIPTOR_REG 0xa4
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#define PLX_DESC_IN_PCI_BIT 0x1 // descriptor is located in pci space (not local space)
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#define PLX_END_OF_CHAIN_BIT 0x2 // end of chain bit
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#define PLX_INTR_TERM_COUNT 0x4 // interrupt when this descriptor's transfer is finished
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#define PLX_XFER_LOCAL_TO_PCI 0x8 // transfer from local to pci bus (not pci to local)
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#define PLX_DMA0_CS_REG 0xa8 // command status register
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#define PLX_DMA1_CS_REG 0xa9
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#define PLX_DMA_EN_BIT 0x1 // enable dma channel
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#define PLX_DMA_START_BIT 0x2 // start dma transfer
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#define PLX_DMA_ABORT_BIT 0x4 // abort dma transfer
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#define PLX_CLEAR_DMA_INTR_BIT 0x8 // clear dma interrupt
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#define PLX_DMA_DONE_BIT 0x10 // transfer done status bit
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#define PLX_DMA0_THRESHOLD_REG 0xb0 // command status register
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/*
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* Accesses near the end of memory can cause the PLX chip
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* to pre-fetch data off of end-of-ram. Limit the size of
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* memory so host-side accesses cannot occur.
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*/
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#define PLX_PREFETCH 32
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/*
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* The PCI Interface, via the PCI-9060 Chip, has up to eight (8) Mailbox
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* Registers. The PUTS (Power-Up Test Suite) handles the board-side
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* interface/interaction using the first 4 registers. Specifications for
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* the use of the full PUTS' command and status interface is contained
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* within a separate SBE PUTS Manual. The Host-Side Device Driver only
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* uses a subset of the full PUTS interface.
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*/
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/*****************************************/
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/*** MAILBOX #(-1) - MEM ACCESS STS ***/
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/*****************************************/
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#define MBX_STS_VALID 0x57584744 /* 'WXGD' */
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#define MBX_STS_DILAV 0x44475857 /* swapped = 'DGXW' */
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/*****************************************/
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/*** MAILBOX #0 - PUTS STATUS ***/
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/*****************************************/
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#define MBX_STS_MASK 0x000000ff /* PUTS Status Register bits */
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#define MBX_STS_TMASK 0x0000000f /* register bits for TEST number */
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#define MBX_STS_PCIRESET 0x00000100 /* Host issued PCI reset request */
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#define MBX_STS_BUSY 0x00000080 /* PUTS is in progress */
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#define MBX_STS_ERROR 0x00000040 /* PUTS has failed */
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#define MBX_STS_RESERVED 0x000000c0 /* Undefined -> status in transition.
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We are in process of changing
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bits; we SET Error bit before
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RESET of Busy bit */
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#define MBX_RESERVED_5 0x00000020 /* FYI: reserved/unused bit */
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#define MBX_RESERVED_4 0x00000010 /* FYI: reserved/unused bit */
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/******************************************/
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/*** MAILBOX #1 - PUTS COMMANDS ***/
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/******************************************/
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/*
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* Any attempt to execute an unimplement command results in the PUTS
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* interface executing a NOOP and continuing as if the offending command
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* completed normally. Note: this supplies a simple method to interrogate
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* mailbox command processing functionality.
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*/
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#define MBX_CMD_MASK 0xffff0000 /* PUTS Command Register bits */
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#define MBX_CMD_ABORTJ 0x85000000 /* abort and jump */
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#define MBX_CMD_RESETP 0x86000000 /* reset and pause at start */
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#define MBX_CMD_PAUSE 0x87000000 /* pause immediately */
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#define MBX_CMD_PAUSEC 0x88000000 /* pause on completion */
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#define MBX_CMD_RESUME 0x89000000 /* resume operation */
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#define MBX_CMD_STEP 0x8a000000 /* single step tests */
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#define MBX_CMD_BSWAP 0x8c000000 /* identify byte swap scheme */
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#define MBX_CMD_BSWAP_0 0x8c000000 /* use scheme 0 */
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#define MBX_CMD_BSWAP_1 0x8c000001 /* use scheme 1 */
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#define MBX_CMD_SETHMS 0x8d000000 /* setup host memory access window
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size */
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#define MBX_CMD_SETHBA 0x8e000000 /* setup host memory access base
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address */
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#define MBX_CMD_MGO 0x8f000000 /* perform memory setup and continue
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(IE. Done) */
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#define MBX_CMD_NOOP 0xFF000000 /* dummy, illegal command */
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/*****************************************/
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/*** MAILBOX #2 - MEMORY SIZE ***/
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/*****************************************/
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#define MBX_MEMSZ_MASK 0xffff0000 /* PUTS Memory Size Register bits */
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#define MBX_MEMSZ_128KB 0x00020000 /* 128 kilobyte board */
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#define MBX_MEMSZ_256KB 0x00040000 /* 256 kilobyte board */
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#define MBX_MEMSZ_512KB 0x00080000 /* 512 kilobyte board */
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#define MBX_MEMSZ_1MB 0x00100000 /* 1 megabyte board */
|
||||
#define MBX_MEMSZ_2MB 0x00200000 /* 2 megabyte board */
|
||||
#define MBX_MEMSZ_4MB 0x00400000 /* 4 megabyte board */
|
||||
#define MBX_MEMSZ_8MB 0x00800000 /* 8 megabyte board */
|
||||
#define MBX_MEMSZ_16MB 0x01000000 /* 16 megabyte board */
|
||||
|
||||
/***************************************/
|
||||
/*** MAILBOX #2 - BOARD TYPE ***/
|
||||
/***************************************/
|
||||
|
||||
#define MBX_BTYPE_MASK 0x0000ffff /* PUTS Board Type Register */
|
||||
#define MBX_BTYPE_FAMILY_MASK 0x0000ff00 /* PUTS Board Family Register */
|
||||
#define MBX_BTYPE_SUBTYPE_MASK 0x000000ff /* PUTS Board Subtype */
|
||||
|
||||
#define MBX_BTYPE_PLX9060 0x00000100 /* PLX family type */
|
||||
#define MBX_BTYPE_PLX9080 0x00000300 /* PLX wanXL100s family type */
|
||||
|
||||
#define MBX_BTYPE_WANXL_4 0x00000104 /* wanXL400, 4-port */
|
||||
#define MBX_BTYPE_WANXL_2 0x00000102 /* wanXL200, 2-port */
|
||||
#define MBX_BTYPE_WANXL_1s 0x00000301 /* wanXL100s, 1-port */
|
||||
#define MBX_BTYPE_WANXL_1t 0x00000401 /* wanXL100T1, 1-port */
|
||||
|
||||
/*****************************************/
|
||||
/*** MAILBOX #3 - SHMQ MAILBOX ***/
|
||||
/*****************************************/
|
||||
|
||||
#define MBX_SMBX_MASK 0x000000ff /* PUTS SHMQ Mailbox bits */
|
||||
|
||||
/***************************************/
|
||||
/*** GENERIC HOST-SIDE DRIVER ***/
|
||||
/***************************************/
|
||||
|
||||
#define MBX_ERR 0
|
||||
#define MBX_OK 1
|
||||
|
||||
/* mailbox check routine - type of testing */
|
||||
#define MBXCHK_STS 0x00 /* check for PUTS status */
|
||||
#define MBXCHK_NOWAIT 0x01 /* dont care about PUTS status */
|
||||
|
||||
/* system allocates this many bytes for address mapping mailbox space */
|
||||
#define MBX_ADDR_SPACE_360 0x80 /* wanXL100s/200/400 */
|
||||
#define MBX_ADDR_MASK_360 (MBX_ADDR_SPACE_360-1)
|
||||
|
||||
static inline int plx9080_abort_dma(void *iobase, unsigned int channel)
|
||||
{
|
||||
void *dma_cs_addr;
|
||||
uint8_t dma_status;
|
||||
const int timeout = 10000;
|
||||
unsigned int i;
|
||||
|
||||
if (channel)
|
||||
dma_cs_addr = iobase + PLX_DMA1_CS_REG;
|
||||
else
|
||||
dma_cs_addr = iobase + PLX_DMA0_CS_REG;
|
||||
|
||||
// abort dma transfer if necessary
|
||||
dma_status = readb(dma_cs_addr);
|
||||
if ((dma_status & PLX_DMA_EN_BIT) == 0) {
|
||||
return 0;
|
||||
}
|
||||
// wait to make sure done bit is zero
|
||||
for (i = 0; (dma_status & PLX_DMA_DONE_BIT) && i < timeout; i++) {
|
||||
comedi_udelay(1);
|
||||
dma_status = readb(dma_cs_addr);
|
||||
}
|
||||
if (i == timeout) {
|
||||
rt_printk
|
||||
("plx9080: cancel() timed out waiting for dma %i done clear\n",
|
||||
channel);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
// disable and abort channel
|
||||
writeb(PLX_DMA_ABORT_BIT, dma_cs_addr);
|
||||
// wait for dma done bit
|
||||
dma_status = readb(dma_cs_addr);
|
||||
for (i = 0; (dma_status & PLX_DMA_DONE_BIT) == 0 && i < timeout; i++) {
|
||||
comedi_udelay(1);
|
||||
dma_status = readb(dma_cs_addr);
|
||||
}
|
||||
if (i == timeout) {
|
||||
rt_printk
|
||||
("plx9080: cancel() timed out waiting for dma %i done set\n",
|
||||
channel);
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* __COMEDI_PLX9080_H */
|
||||
2283
drivers/staging/comedi/drivers/rtd520.c
Normal file
2283
drivers/staging/comedi/drivers/rtd520.c
Normal file
File diff suppressed because it is too large
Load diff
412
drivers/staging/comedi/drivers/rtd520.h
Normal file
412
drivers/staging/comedi/drivers/rtd520.h
Normal file
|
|
@ -0,0 +1,412 @@
|
|||
/*
|
||||
comedi/drivers/rtd520.h
|
||||
Comedi driver defines for Real Time Devices (RTD) PCI4520/DM7520
|
||||
|
||||
COMEDI - Linux Control and Measurement Device Interface
|
||||
Copyright (C) 2001 David A. Schleef <ds@schleef.org>
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
/*
|
||||
Created by Dan Christian, NASA Ames Research Center.
|
||||
See board notes in rtd520.c
|
||||
*/
|
||||
|
||||
/*
|
||||
LAS0 Runtime Area
|
||||
Local Address Space 0 Offset Read Function Write Function
|
||||
*/
|
||||
#define LAS0_SPARE_00 0x0000 // - -
|
||||
#define LAS0_SPARE_04 0x0004 // - -
|
||||
#define LAS0_USER_IO 0x0008 // Read User Inputs Write User Outputs
|
||||
#define LAS0_SPARE_0C 0x000C // - -
|
||||
#define LAS0_ADC 0x0010 // Read FIFO Status Software A/D Start
|
||||
#define LAS0_DAC1 0x0014 // - Software D/A1 Update
|
||||
#define LAS0_DAC2 0x0018 // - Software D/A2 Update
|
||||
#define LAS0_SPARE_1C 0x001C // - -
|
||||
#define LAS0_SPARE_20 0x0020 // - -
|
||||
#define LAS0_DAC 0x0024 // - Software Simultaneous D/A1 and D/A2 Update
|
||||
#define LAS0_PACER 0x0028 // Software Pacer Start Software Pacer Stop
|
||||
#define LAS0_TIMER 0x002C // Read Timer Counters Status HDIN Software Trigger
|
||||
#define LAS0_IT 0x0030 // Read Interrupt Status Write Interrupt Enable Mask Register
|
||||
#define LAS0_CLEAR 0x0034 // Clear ITs set by Clear Mask Set Interrupt Clear Mask
|
||||
#define LAS0_OVERRUN 0x0038 // Read pending interrupts Clear Overrun Register
|
||||
#define LAS0_SPARE_3C 0x003C // - -
|
||||
|
||||
/*
|
||||
LAS0 Runtime Area Timer/Counter,Dig.IO
|
||||
Name Local Address Function
|
||||
*/
|
||||
#define LAS0_PCLK 0x0040 // Pacer Clock value (24bit) Pacer Clock load (24bit)
|
||||
#define LAS0_BCLK 0x0044 // Burst Clock value (10bit) Burst Clock load (10bit)
|
||||
#define LAS0_ADC_SCNT 0x0048 // A/D Sample counter value (10bit) A/D Sample counter load (10bit)
|
||||
#define LAS0_DAC1_UCNT 0x004C // D/A1 Update counter value (10 bit) D/A1 Update counter load (10bit)
|
||||
#define LAS0_DAC2_UCNT 0x0050 // D/A2 Update counter value (10 bit) D/A2 Update counter load (10bit)
|
||||
#define LAS0_DCNT 0x0054 // Delay counter value (16 bit) Delay counter load (16bit)
|
||||
#define LAS0_ACNT 0x0058 // About counter value (16 bit) About counter load (16bit)
|
||||
#define LAS0_DAC_CLK 0x005C // DAC clock value (16bit) DAC clock load (16bit)
|
||||
#define LAS0_UTC0 0x0060 // 8254 TC Counter 0 User TC 0 value Load count in TC Counter 0
|
||||
#define LAS0_UTC1 0x0064 // 8254 TC Counter 1 User TC 1 value Load count in TC Counter 1
|
||||
#define LAS0_UTC2 0x0068 // 8254 TC Counter 2 User TC 2 value Load count in TC Counter 2
|
||||
#define LAS0_UTC_CTRL 0x006C // 8254 TC Control Word Program counter mode for TC
|
||||
#define LAS0_DIO0 0x0070 // Digital I/O Port 0 Read Port Digital I/O Port 0 Write Port
|
||||
#define LAS0_DIO1 0x0074 // Digital I/O Port 1 Read Port Digital I/O Port 1 Write Port
|
||||
#define LAS0_DIO0_CTRL 0x0078 // Clear digital IRQ status flag/read Clear digital chip/program Port 0
|
||||
#define LAS0_DIO_STATUS 0x007C // Read Digital I/O Status word Program digital control register &
|
||||
|
||||
/*
|
||||
LAS0 Setup Area
|
||||
Name Local Address Function
|
||||
*/
|
||||
#define LAS0_BOARD_RESET 0x0100 // Board reset
|
||||
#define LAS0_DMA0_SRC 0x0104 // DMA 0 Sources select
|
||||
#define LAS0_DMA1_SRC 0x0108 // DMA 1 Sources select
|
||||
#define LAS0_ADC_CONVERSION 0x010C // A/D Conversion Signal select
|
||||
#define LAS0_BURST_START 0x0110 // Burst Clock Start Trigger select
|
||||
#define LAS0_PACER_START 0x0114 // Pacer Clock Start Trigger select
|
||||
#define LAS0_PACER_STOP 0x0118 // Pacer Clock Stop Trigger select
|
||||
#define LAS0_ACNT_STOP_ENABLE 0x011C // About Counter Stop Enable
|
||||
#define LAS0_PACER_REPEAT 0x0120 // Pacer Start Trigger Mode select
|
||||
#define LAS0_DIN_START 0x0124 // High Speed Digital Input Sampling Signal select
|
||||
#define LAS0_DIN_FIFO_CLEAR 0x0128 // Digital Input FIFO Clear
|
||||
#define LAS0_ADC_FIFO_CLEAR 0x012C // A/D FIFO Clear
|
||||
#define LAS0_CGT_WRITE 0x0130 // Channel Gain Table Write
|
||||
#define LAS0_CGL_WRITE 0x0134 // Channel Gain Latch Write
|
||||
#define LAS0_CG_DATA 0x0138 // Digital Table Write
|
||||
#define LAS0_CGT_ENABLE 0x013C // Channel Gain Table Enable
|
||||
#define LAS0_CG_ENABLE 0x0140 // Digital Table Enable
|
||||
#define LAS0_CGT_PAUSE 0x0144 // Table Pause Enable
|
||||
#define LAS0_CGT_RESET 0x0148 // Reset Channel Gain Table
|
||||
#define LAS0_CGT_CLEAR 0x014C // Clear Channel Gain Table
|
||||
#define LAS0_DAC1_CTRL 0x0150 // D/A1 output type/range
|
||||
#define LAS0_DAC1_SRC 0x0154 // D/A1 update source
|
||||
#define LAS0_DAC1_CYCLE 0x0158 // D/A1 cycle mode
|
||||
#define LAS0_DAC1_RESET 0x015C // D/A1 FIFO reset
|
||||
#define LAS0_DAC1_FIFO_CLEAR 0x0160 // D/A1 FIFO clear
|
||||
#define LAS0_DAC2_CTRL 0x0164 // D/A2 output type/range
|
||||
#define LAS0_DAC2_SRC 0x0168 // D/A2 update source
|
||||
#define LAS0_DAC2_CYCLE 0x016C // D/A2 cycle mode
|
||||
#define LAS0_DAC2_RESET 0x0170 // D/A2 FIFO reset
|
||||
#define LAS0_DAC2_FIFO_CLEAR 0x0174 // D/A2 FIFO clear
|
||||
#define LAS0_ADC_SCNT_SRC 0x0178 // A/D Sample Counter Source select
|
||||
#define LAS0_PACER_SELECT 0x0180 // Pacer Clock select
|
||||
#define LAS0_SBUS0_SRC 0x0184 // SyncBus 0 Source select
|
||||
#define LAS0_SBUS0_ENABLE 0x0188 // SyncBus 0 enable
|
||||
#define LAS0_SBUS1_SRC 0x018C // SyncBus 1 Source select
|
||||
#define LAS0_SBUS1_ENABLE 0x0190 // SyncBus 1 enable
|
||||
#define LAS0_SBUS2_SRC 0x0198 // SyncBus 2 Source select
|
||||
#define LAS0_SBUS2_ENABLE 0x019C // SyncBus 2 enable
|
||||
#define LAS0_ETRG_POLARITY 0x01A4 // External Trigger polarity select
|
||||
#define LAS0_EINT_POLARITY 0x01A8 // External Interrupt polarity select
|
||||
#define LAS0_UTC0_CLOCK 0x01AC // UTC0 Clock select
|
||||
#define LAS0_UTC0_GATE 0x01B0 // UTC0 Gate select
|
||||
#define LAS0_UTC1_CLOCK 0x01B4 // UTC1 Clock select
|
||||
#define LAS0_UTC1_GATE 0x01B8 // UTC1 Gate select
|
||||
#define LAS0_UTC2_CLOCK 0x01BC // UTC2 Clock select
|
||||
#define LAS0_UTC2_GATE 0x01C0 // UTC2 Gate select
|
||||
#define LAS0_UOUT0_SELECT 0x01C4 // User Output 0 source select
|
||||
#define LAS0_UOUT1_SELECT 0x01C8 // User Output 1 source select
|
||||
#define LAS0_DMA0_RESET 0x01CC // DMA0 Request state machine reset
|
||||
#define LAS0_DMA1_RESET 0x01D0 // DMA1 Request state machine reset
|
||||
|
||||
/*
|
||||
LAS1
|
||||
Name Local Address Function
|
||||
*/
|
||||
#define LAS1_ADC_FIFO 0x0000 // Read A/D FIFO (16bit) -
|
||||
#define LAS1_HDIO_FIFO 0x0004 // Read High Speed Digital Input FIFO (16bit) -
|
||||
#define LAS1_DAC1_FIFO 0x0008 // - Write D/A1 FIFO (16bit)
|
||||
#define LAS1_DAC2_FIFO 0x000C // - Write D/A2 FIFO (16bit)
|
||||
|
||||
/*
|
||||
LCFG: PLX 9080 local config & runtime registers
|
||||
Name Local Address Function
|
||||
*/
|
||||
#define LCFG_ITCSR 0x0068 // INTCSR, Interrupt Control/Status Register
|
||||
#define LCFG_DMAMODE0 0x0080 // DMA Channel 0 Mode Register
|
||||
#define LCFG_DMAPADR0 0x0084 // DMA Channel 0 PCI Address Register
|
||||
#define LCFG_DMALADR0 0x0088 // DMA Channel 0 Local Address Reg
|
||||
#define LCFG_DMASIZ0 0x008C // DMA Channel 0 Transfer Size (Bytes) Register
|
||||
#define LCFG_DMADPR0 0x0090 // DMA Channel 0 Descriptor Pointer Register
|
||||
#define LCFG_DMAMODE1 0x0094 // DMA Channel 1 Mode Register
|
||||
#define LCFG_DMAPADR1 0x0098 // DMA Channel 1 PCI Address Register
|
||||
#define LCFG_DMALADR1 0x009C // DMA Channel 1 Local Address Register
|
||||
#define LCFG_DMASIZ1 0x00A0 // DMA Channel 1 Transfer Size (Bytes) Register
|
||||
#define LCFG_DMADPR1 0x00A4 // DMA Channel 1 Descriptor Pointer Register
|
||||
#define LCFG_DMACSR0 0x00A8 // DMA Channel 0 Command/Status Register
|
||||
#define LCFG_DMACSR1 0x00A9 // DMA Channel 0 Command/Status Register
|
||||
#define LCFG_DMAARB 0x00AC // DMA Arbitration Register
|
||||
#define LCFG_DMATHR 0x00B0 // DMA Threshold Register
|
||||
|
||||
/*======================================================================
|
||||
Resister bit definitions
|
||||
======================================================================*/
|
||||
|
||||
// FIFO Status Word Bits (RtdFifoStatus)
|
||||
#define FS_DAC1_NOT_EMPTY 0x0001 // D0 - DAC1 FIFO not empty
|
||||
#define FS_DAC1_HEMPTY 0x0002 // D1 - DAC1 FIFO half empty
|
||||
#define FS_DAC1_NOT_FULL 0x0004 // D2 - DAC1 FIFO not full
|
||||
#define FS_DAC2_NOT_EMPTY 0x0010 // D4 - DAC2 FIFO not empty
|
||||
#define FS_DAC2_HEMPTY 0x0020 // D5 - DAC2 FIFO half empty
|
||||
#define FS_DAC2_NOT_FULL 0x0040 // D6 - DAC2 FIFO not full
|
||||
#define FS_ADC_NOT_EMPTY 0x0100 // D8 - ADC FIFO not empty
|
||||
#define FS_ADC_HEMPTY 0x0200 // D9 - ADC FIFO half empty
|
||||
#define FS_ADC_NOT_FULL 0x0400 // D10 - ADC FIFO not full
|
||||
#define FS_DIN_NOT_EMPTY 0x1000 // D12 - DIN FIFO not empty
|
||||
#define FS_DIN_HEMPTY 0x2000 // D13 - DIN FIFO half empty
|
||||
#define FS_DIN_NOT_FULL 0x4000 // D14 - DIN FIFO not full
|
||||
|
||||
// Timer Status Word Bits (GetTimerStatus)
|
||||
#define TS_PCLK_GATE 0x0001
|
||||
// D0 - Pacer Clock Gate [0 - gated, 1 - enabled]
|
||||
#define TS_BCLK_GATE 0x0002
|
||||
// D1 - Burst Clock Gate [0 - disabled, 1 - running]
|
||||
#define TS_DCNT_GATE 0x0004
|
||||
// D2 - Pacer Clock Delayed Start Trigger [0 - delay over, 1 - delay in
|
||||
// progress]
|
||||
#define TS_ACNT_GATE 0x0008
|
||||
// D3 - Pacer Clock About Trigger [0 - completed, 1 - in progress]
|
||||
#define TS_PCLK_RUN 0x0010
|
||||
// D4 - Pacer Clock Shutdown Flag [0 - Pacer Clock cannot be start
|
||||
// triggered only by Software Pacer Start Command, 1 - Pacer Clock can
|
||||
// be start triggered]
|
||||
|
||||
// External Trigger polarity select
|
||||
// External Interrupt polarity select
|
||||
#define POL_POSITIVE 0x0 // positive edge
|
||||
#define POL_NEGATIVE 0x1 // negative edge
|
||||
|
||||
// User Output Signal select (SetUout0Source, SetUout1Source)
|
||||
#define UOUT_ADC 0x0 // A/D Conversion Signal
|
||||
#define UOUT_DAC1 0x1 // D/A1 Update
|
||||
#define UOUT_DAC2 0x2 // D/A2 Update
|
||||
#define UOUT_SOFTWARE 0x3 // Software Programmable
|
||||
|
||||
// Pacer clock select (SetPacerSource)
|
||||
#define PCLK_INTERNAL 1 // Internal Pacer Clock
|
||||
#define PCLK_EXTERNAL 0 // External Pacer Clock
|
||||
|
||||
// A/D Sample Counter Sources (SetAdcntSource, SetupSampleCounter)
|
||||
#define ADC_SCNT_CGT_RESET 0x0 // needs restart with StartPacer
|
||||
#define ADC_SCNT_FIFO_WRITE 0x1
|
||||
|
||||
// A/D Conversion Signal Select (for SetConversionSelect)
|
||||
#define ADC_START_SOFTWARE 0x0 // Software A/D Start
|
||||
#define ADC_START_PCLK 0x1 // Pacer Clock (Ext. Int. see Func.509)
|
||||
#define ADC_START_BCLK 0x2 // Burst Clock
|
||||
#define ADC_START_DIGITAL_IT 0x3 // Digital Interrupt
|
||||
#define ADC_START_DAC1_MARKER1 0x4 // D/A 1 Data Marker 1
|
||||
#define ADC_START_DAC2_MARKER1 0x5 // D/A 2 Data Marker 1
|
||||
#define ADC_START_SBUS0 0x6 // SyncBus 0
|
||||
#define ADC_START_SBUS1 0x7 // SyncBus 1
|
||||
#define ADC_START_SBUS2 0x8 // SyncBus 2
|
||||
|
||||
// Burst Clock start trigger select (SetBurstStart)
|
||||
#define BCLK_START_SOFTWARE 0x0 // Software A/D Start (StartBurst)
|
||||
#define BCLK_START_PCLK 0x1 // Pacer Clock
|
||||
#define BCLK_START_ETRIG 0x2 // External Trigger
|
||||
#define BCLK_START_DIGITAL_IT 0x3 // Digital Interrupt
|
||||
#define BCLK_START_SBUS0 0x4 // SyncBus 0
|
||||
#define BCLK_START_SBUS1 0x5 // SyncBus 1
|
||||
#define BCLK_START_SBUS2 0x6 // SyncBus 2
|
||||
|
||||
// Pacer Clock start trigger select (SetPacerStart)
|
||||
#define PCLK_START_SOFTWARE 0x0 // Software Pacer Start (StartPacer)
|
||||
#define PCLK_START_ETRIG 0x1 // External trigger
|
||||
#define PCLK_START_DIGITAL_IT 0x2 // Digital interrupt
|
||||
#define PCLK_START_UTC2 0x3 // User TC 2 out
|
||||
#define PCLK_START_SBUS0 0x4 // SyncBus 0
|
||||
#define PCLK_START_SBUS1 0x5 // SyncBus 1
|
||||
#define PCLK_START_SBUS2 0x6 // SyncBus 2
|
||||
#define PCLK_START_D_SOFTWARE 0x8 // Delayed Software Pacer Start
|
||||
#define PCLK_START_D_ETRIG 0x9 // Delayed external trigger
|
||||
#define PCLK_START_D_DIGITAL_IT 0xA // Delayed digital interrupt
|
||||
#define PCLK_START_D_UTC2 0xB // Delayed User TC 2 out
|
||||
#define PCLK_START_D_SBUS0 0xC // Delayed SyncBus 0
|
||||
#define PCLK_START_D_SBUS1 0xD // Delayed SyncBus 1
|
||||
#define PCLK_START_D_SBUS2 0xE // Delayed SyncBus 2
|
||||
#define PCLK_START_ETRIG_GATED 0xF // External Trigger Gated controlled mode
|
||||
|
||||
// Pacer Clock Stop Trigger select (SetPacerStop)
|
||||
#define PCLK_STOP_SOFTWARE 0x0 // Software Pacer Stop (StopPacer)
|
||||
#define PCLK_STOP_ETRIG 0x1 // External Trigger
|
||||
#define PCLK_STOP_DIGITAL_IT 0x2 // Digital Interrupt
|
||||
#define PCLK_STOP_ACNT 0x3 // About Counter
|
||||
#define PCLK_STOP_UTC2 0x4 // User TC2 out
|
||||
#define PCLK_STOP_SBUS0 0x5 // SyncBus 0
|
||||
#define PCLK_STOP_SBUS1 0x6 // SyncBus 1
|
||||
#define PCLK_STOP_SBUS2 0x7 // SyncBus 2
|
||||
#define PCLK_STOP_A_SOFTWARE 0x8 // About Software Pacer Stop
|
||||
#define PCLK_STOP_A_ETRIG 0x9 // About External Trigger
|
||||
#define PCLK_STOP_A_DIGITAL_IT 0xA // About Digital Interrupt
|
||||
#define PCLK_STOP_A_UTC2 0xC // About User TC2 out
|
||||
#define PCLK_STOP_A_SBUS0 0xD // About SyncBus 0
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||||
#define PCLK_STOP_A_SBUS1 0xE // About SyncBus 1
|
||||
#define PCLK_STOP_A_SBUS2 0xF // About SyncBus 2
|
||||
|
||||
// About Counter Stop Enable
|
||||
#define ACNT_STOP 0x0 // stop enable
|
||||
#define ACNT_NO_STOP 0x1 // stop disabled
|
||||
|
||||
// DAC update source (SetDAC1Start & SetDAC2Start)
|
||||
#define DAC_START_SOFTWARE 0x0 // Software Update
|
||||
#define DAC_START_CGT 0x1 // CGT controlled Update
|
||||
#define DAC_START_DAC_CLK 0x2 // D/A Clock
|
||||
#define DAC_START_EPCLK 0x3 // External Pacer Clock
|
||||
#define DAC_START_SBUS0 0x4 // SyncBus 0
|
||||
#define DAC_START_SBUS1 0x5 // SyncBus 1
|
||||
#define DAC_START_SBUS2 0x6 // SyncBus 2
|
||||
|
||||
// DAC Cycle Mode (SetDAC1Cycle, SetDAC2Cycle, SetupDAC)
|
||||
#define DAC_CYCLE_SINGLE 0x0 // not cycle
|
||||
#define DAC_CYCLE_MULTI 0x1 // cycle
|
||||
|
||||
// 8254 Operation Modes (Set8254Mode, SetupTimerCounter)
|
||||
#define M8254_EVENT_COUNTER 0 // Event Counter
|
||||
#define M8254_HW_ONE_SHOT 1 // Hardware-Retriggerable One-Shot
|
||||
#define M8254_RATE_GENERATOR 2 // Rate Generator
|
||||
#define M8254_SQUARE_WAVE 3 // Square Wave Mode
|
||||
#define M8254_SW_STROBE 4 // Software Triggered Strobe
|
||||
#define M8254_HW_STROBE 5 // Hardware Triggered Strobe (Retriggerable)
|
||||
|
||||
// User Timer/Counter 0 Clock Select (SetUtc0Clock)
|
||||
#define CUTC0_8MHZ 0x0 // 8MHz
|
||||
#define CUTC0_EXT_TC_CLOCK1 0x1 // Ext. TC Clock 1
|
||||
#define CUTC0_EXT_TC_CLOCK2 0x2 // Ext. TC Clock 2
|
||||
#define CUTC0_EXT_PCLK 0x3 // Ext. Pacer Clock
|
||||
|
||||
// User Timer/Counter 1 Clock Select (SetUtc1Clock)
|
||||
#define CUTC1_8MHZ 0x0 // 8MHz
|
||||
#define CUTC1_EXT_TC_CLOCK1 0x1 // Ext. TC Clock 1
|
||||
#define CUTC1_EXT_TC_CLOCK2 0x2 // Ext. TC Clock 2
|
||||
#define CUTC1_EXT_PCLK 0x3 // Ext. Pacer Clock
|
||||
#define CUTC1_UTC0_OUT 0x4 // User Timer/Counter 0 out
|
||||
#define CUTC1_DIN_SIGNAL 0x5 // High-Speed Digital Input Sampling signal
|
||||
|
||||
// User Timer/Counter 2 Clock Select (SetUtc2Clock)
|
||||
#define CUTC2_8MHZ 0x0 // 8MHz
|
||||
#define CUTC2_EXT_TC_CLOCK1 0x1 // Ext. TC Clock 1
|
||||
#define CUTC2_EXT_TC_CLOCK2 0x2 // Ext. TC Clock 2
|
||||
#define CUTC2_EXT_PCLK 0x3 // Ext. Pacer Clock
|
||||
#define CUTC2_UTC1_OUT 0x4 // User Timer/Counter 1 out
|
||||
|
||||
// User Timer/Counter 0 Gate Select (SetUtc0Gate)
|
||||
#define GUTC0_NOT_GATED 0x0 // Not gated
|
||||
#define GUTC0_GATED 0x1 // Gated
|
||||
#define GUTC0_EXT_TC_GATE1 0x2 // Ext. TC Gate 1
|
||||
#define GUTC0_EXT_TC_GATE2 0x3 // Ext. TC Gate 2
|
||||
|
||||
// User Timer/Counter 1 Gate Select (SetUtc1Gate)
|
||||
#define GUTC1_NOT_GATED 0x0 // Not gated
|
||||
#define GUTC1_GATED 0x1 // Gated
|
||||
#define GUTC1_EXT_TC_GATE1 0x2 // Ext. TC Gate 1
|
||||
#define GUTC1_EXT_TC_GATE2 0x3 // Ext. TC Gate 2
|
||||
#define GUTC1_UTC0_OUT 0x4 // User Timer/Counter 0 out
|
||||
|
||||
// User Timer/Counter 2 Gate Select (SetUtc2Gate)
|
||||
#define GUTC2_NOT_GATED 0x0 // Not gated
|
||||
#define GUTC2_GATED 0x1 // Gated
|
||||
#define GUTC2_EXT_TC_GATE1 0x2 // Ext. TC Gate 1
|
||||
#define GUTC2_EXT_TC_GATE2 0x3 // Ext. TC Gate 2
|
||||
#define GUTC2_UTC1_OUT 0x4 // User Timer/Counter 1 out
|
||||
|
||||
// Interrupt Source Masks (SetITMask, ClearITMask, GetITStatus)
|
||||
#define IRQM_ADC_FIFO_WRITE 0x0001 // ADC FIFO Write
|
||||
#define IRQM_CGT_RESET 0x0002 // Reset CGT
|
||||
#define IRQM_CGT_PAUSE 0x0008 // Pause CGT
|
||||
#define IRQM_ADC_ABOUT_CNT 0x0010 // About Counter out
|
||||
#define IRQM_ADC_DELAY_CNT 0x0020 // Delay Counter out
|
||||
#define IRQM_ADC_SAMPLE_CNT 0x0040 // ADC Sample Counter
|
||||
#define IRQM_DAC1_UCNT 0x0080 // DAC1 Update Counter
|
||||
#define IRQM_DAC2_UCNT 0x0100 // DAC2 Update Counter
|
||||
#define IRQM_UTC1 0x0200 // User TC1 out
|
||||
#define IRQM_UTC1_INV 0x0400 // User TC1 out, inverted
|
||||
#define IRQM_UTC2 0x0800 // User TC2 out
|
||||
#define IRQM_DIGITAL_IT 0x1000 // Digital Interrupt
|
||||
#define IRQM_EXTERNAL_IT 0x2000 // External Interrupt
|
||||
#define IRQM_ETRIG_RISING 0x4000 // External Trigger rising-edge
|
||||
#define IRQM_ETRIG_FALLING 0x8000 // External Trigger falling-edge
|
||||
|
||||
// DMA Request Sources (LAS0)
|
||||
#define DMAS_DISABLED 0x0 // DMA Disabled
|
||||
#define DMAS_ADC_SCNT 0x1 // ADC Sample Counter
|
||||
#define DMAS_DAC1_UCNT 0x2 // D/A1 Update Counter
|
||||
#define DMAS_DAC2_UCNT 0x3 // D/A2 Update Counter
|
||||
#define DMAS_UTC1 0x4 // User TC1 out
|
||||
#define DMAS_ADFIFO_HALF_FULL 0x8 // A/D FIFO half full
|
||||
#define DMAS_DAC1_FIFO_HALF_EMPTY 0x9 // D/A1 FIFO half empty
|
||||
#define DMAS_DAC2_FIFO_HALF_EMPTY 0xA // D/A2 FIFO half empty
|
||||
|
||||
// DMA Local Addresses (0x40000000+LAS1 offset)
|
||||
#define DMALADDR_ADC 0x40000000 // A/D FIFO
|
||||
#define DMALADDR_HDIN 0x40000004 // High Speed Digital Input FIFO
|
||||
#define DMALADDR_DAC1 0x40000008 // D/A1 FIFO
|
||||
#define DMALADDR_DAC2 0x4000000C // D/A2 FIFO
|
||||
|
||||
// Port 0 compare modes (SetDIO0CompareMode)
|
||||
#define DIO_MODE_EVENT 0 // Event Mode
|
||||
#define DIO_MODE_MATCH 1 // Match Mode
|
||||
|
||||
// Digital Table Enable (Port 1 disable)
|
||||
#define DTBL_DISABLE 0 // Enable Digital Table
|
||||
#define DTBL_ENABLE 1 // Disable Digital Table
|
||||
|
||||
// Sampling Signal for High Speed Digital Input (SetHdinStart)
|
||||
#define HDIN_SOFTWARE 0x0 // Software Trigger
|
||||
#define HDIN_ADC 0x1 // A/D Conversion Signal
|
||||
#define HDIN_UTC0 0x2 // User TC out 0
|
||||
#define HDIN_UTC1 0x3 // User TC out 1
|
||||
#define HDIN_UTC2 0x4 // User TC out 2
|
||||
#define HDIN_EPCLK 0x5 // External Pacer Clock
|
||||
#define HDIN_ETRG 0x6 // External Trigger
|
||||
|
||||
// Channel Gain Table / Channel Gain Latch
|
||||
#define CSC_LATCH 0 // Channel Gain Latch mode
|
||||
#define CSC_CGT 1 // Channel Gain Table mode
|
||||
|
||||
// Channel Gain Table Pause Enable
|
||||
#define CGT_PAUSE_DISABLE 0 // Channel Gain Table Pause Disable
|
||||
#define CGT_PAUSE_ENABLE 1 // Channel Gain Table Pause Enable
|
||||
|
||||
// DAC output type/range (p63)
|
||||
#define AOUT_UNIP5 0 // 0..+5 Volt
|
||||
#define AOUT_UNIP10 1 // 0..+10 Volt
|
||||
#define AOUT_BIP5 2 // -5..+5 Volt
|
||||
#define AOUT_BIP10 3 // -10..+10 Volt
|
||||
|
||||
// Ghannel Gain Table field definitions (p61)
|
||||
// Gain
|
||||
#define GAIN1 0
|
||||
#define GAIN2 1
|
||||
#define GAIN4 2
|
||||
#define GAIN8 3
|
||||
#define GAIN16 4
|
||||
#define GAIN32 5
|
||||
#define GAIN64 6
|
||||
#define GAIN128 7
|
||||
|
||||
// Input range/polarity
|
||||
#define AIN_BIP5 0 // -5..+5 Volt
|
||||
#define AIN_BIP10 1 // -10..+10 Volt
|
||||
#define AIN_UNIP10 2 // 0..+10 Volt
|
||||
|
||||
// non referenced single ended select bit
|
||||
#define NRSE_AGND 0 // AGND referenced SE input
|
||||
#define NRSE_AINS 1 // AIN SENSE referenced SE input
|
||||
|
||||
// single ended vs differential
|
||||
#define GND_SE 0 // Single-Ended
|
||||
#define GND_DIFF 1 // Differential
|
||||
Loading…
Reference in a new issue