tools/include: Sync x86 CPU feature headers with the kernel sources
To pick up the changes from:598c2fafc0
("perf/x86/amd/lbr: Use freeze based on availability")7f274e609f
("x86/cpufeatures: Add new word for scattered features") This should address these tools/perf build warnings: Warning: Kernel ABI header differences: diff -u tools/arch/x86/include/asm/disabled-features.h arch/x86/include/asm/disabled-features.h diff -u tools/arch/x86/include/asm/required-features.h arch/x86/include/asm/required-features.h diff -u tools/arch/x86/include/asm/cpufeatures.h arch/x86/include/asm/cpufeatures.h Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: x86@kernel.org Signed-off-by: Namhyung Kim <namhyung@kernel.org> Link: https://lore.kernel.org/r/20240408185520.1550865-6-namhyung@kernel.org
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3 changed files with 23 additions and 8 deletions
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@ -13,7 +13,7 @@
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/*
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/*
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* Defines x86 CPU feature bits
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* Defines x86 CPU feature bits
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*/
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*/
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#define NCAPINTS 21 /* N 32-bit words worth of info */
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#define NCAPINTS 22 /* N 32-bit words worth of info */
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#define NBUGINTS 2 /* N 32-bit bug flags */
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#define NBUGINTS 2 /* N 32-bit bug flags */
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/*
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/*
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@ -81,10 +81,8 @@
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#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
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#define X86_FEATURE_K6_MTRR ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
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#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CYRIX_ARR ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
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/* CPU types for specific tunings: */
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#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
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#define X86_FEATURE_K8 ( 3*32+ 4) /* "" Opteron, Athlon64 */
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/* FREE, was #define X86_FEATURE_K7 ( 3*32+ 5) "" Athlon */
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#define X86_FEATURE_ZEN5 ( 3*32+ 5) /* "" CPU based on Zen5 microarchitecture */
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#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
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#define X86_FEATURE_P3 ( 3*32+ 6) /* "" P3 */
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#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
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#define X86_FEATURE_P4 ( 3*32+ 7) /* "" P4 */
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#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
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#define X86_FEATURE_CONSTANT_TSC ( 3*32+ 8) /* TSC ticks at a constant rate */
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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#define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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#define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */
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#define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
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#define X86_FEATURE_AMD_LBR_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */
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/* FREE, was #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) "" LFENCE synchronizes RDTSC */
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#define X86_FEATURE_CLEAR_CPU_BUF ( 3*32+18) /* "" Clear CPU buffers using VERW */
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#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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#define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */
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#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
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#define X86_FEATURE_ALWAYS ( 3*32+21) /* "" Always-present feature */
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#define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
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#define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */
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#define X86_FEATURE_SRSO_NO (20*32+29) /* "" CPU is not affected by SRSO */
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#define X86_FEATURE_SRSO_NO (20*32+29) /* "" CPU is not affected by SRSO */
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/*
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* Extended auxiliary flags: Linux defined - for features scattered in various
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* CPUID levels like 0x80000022, etc.
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*
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* Reuse free bits when adding new feature flags!
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*/
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#define X86_FEATURE_AMD_LBR_PMC_FREEZE (21*32+ 0) /* AMD LBR and PMC Freeze */
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/*
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/*
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* BUG word(s)
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* BUG word(s)
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*/
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*/
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/* BUG word 2 */
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/* BUG word 2 */
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#define X86_BUG_SRSO X86_BUG(1*32 + 0) /* AMD SRSO bug */
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#define X86_BUG_SRSO X86_BUG(1*32 + 0) /* AMD SRSO bug */
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#define X86_BUG_DIV0 X86_BUG(1*32 + 1) /* AMD DIV0 speculation bug */
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#define X86_BUG_DIV0 X86_BUG(1*32 + 1) /* AMD DIV0 speculation bug */
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#define X86_BUG_RFDS X86_BUG(1*32 + 2) /* CPU is vulnerable to Register File Data Sampling */
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#endif /* _ASM_X86_CPUFEATURES_H */
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#endif /* _ASM_X86_CPUFEATURES_H */
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# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31))
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# define DISABLE_FRED (1 << (X86_FEATURE_FRED & 31))
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#endif
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#endif
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#ifdef CONFIG_KVM_AMD_SEV
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#define DISABLE_SEV_SNP 0
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#else
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#define DISABLE_SEV_SNP (1 << (X86_FEATURE_SEV_SNP & 31))
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#endif
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/*
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/*
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* Make sure to add features to the correct mask
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* Make sure to add features to the correct mask
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*/
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*/
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DISABLE_ENQCMD)
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DISABLE_ENQCMD)
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#define DISABLED_MASK17 0
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#define DISABLED_MASK17 0
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#define DISABLED_MASK18 (DISABLE_IBT)
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#define DISABLED_MASK18 (DISABLE_IBT)
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#define DISABLED_MASK19 0
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#define DISABLED_MASK19 (DISABLE_SEV_SNP)
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#define DISABLED_MASK20 0
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#define DISABLED_MASK20 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
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#define DISABLED_MASK21 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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#endif /* _ASM_X86_DISABLED_FEATURES_H */
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK19 0
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#define REQUIRED_MASK19 0
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#define REQUIRED_MASK20 0
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#define REQUIRED_MASK20 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
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#define REQUIRED_MASK21 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22)
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */
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