clk: remove s3c24xx driver
The s3c24xx platform is gone, so the clk driver can be removed as well. Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
0b14558977
commit
594b3caeaf
8 changed files with 0 additions and 1634 deletions
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@ -18440,7 +18440,6 @@ F: include/dt-bindings/clock/s3c*.h
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F: include/dt-bindings/clock/s5p*.h
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F: include/dt-bindings/clock/samsung,*.h
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F: include/linux/clk/samsung.h
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F: include/linux/platform_data/clk-s3c2410.h
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SAMSUNG SPI DRIVERS
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M: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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@ -94,38 +94,6 @@ config EXYNOS_CLKOUT
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status of the certains clocks from SoC, but it could also be tied to
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other devices as an input clock.
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# For S3C24XX platforms, select following symbols:
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config S3C2410_COMMON_CLK
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bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
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select COMMON_CLK_SAMSUNG
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help
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Support for the clock controller present on the Samsung
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S3C2410/S3C2440/S3C2442 SoCs. Choose Y here only if you build for
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this SoC.
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config S3C2410_COMMON_DCLK
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bool
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select COMMON_CLK_SAMSUNG
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select REGMAP_MMIO
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help
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Support for the dclk clock controller present on the Samsung
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S3C2410/S3C2412/S3C2440/S3C2443 SoCs. Choose Y here only if you build
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for this SoC.
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config S3C2412_COMMON_CLK
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bool "Samsung S3C2412 clock controller support" if COMPILE_TEST
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select COMMON_CLK_SAMSUNG
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help
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Support for the clock controller present on the Samsung S3C2412 SoCs.
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Choose Y here only if you build for this SoC.
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config S3C2443_COMMON_CLK
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bool "Samsung S3C2443 clock controller support" if COMPILE_TEST
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select COMMON_CLK_SAMSUNG
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help
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Support for the clock controller present on the Samsung
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S3C2416/S3C2443 SoCs. Choose Y here only if you build for this SoC.
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config TESLA_FSD_COMMON_CLK
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bool "Tesla FSD clock controller support" if COMPILE_TEST
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depends on COMMON_CLK_SAMSUNG
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@ -21,10 +21,6 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
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obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
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obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
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obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
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obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
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obj-$(CONFIG_S3C2443_COMMON_CLK)+= clk-s3c2443.o
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obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
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obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o
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obj-$(CONFIG_TESLA_FSD_COMMON_CLK) += clk-fsd.o
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@ -1,440 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
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*
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* Common Clock Framework support for s3c24xx external clock output.
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*/
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#include <linux/clkdev.h>
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/platform_data/clk-s3c2410.h>
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#include <linux/module.h>
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#include "clk.h"
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#define MUX_DCLK0 0
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#define MUX_DCLK1 1
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#define DIV_DCLK0 2
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#define DIV_DCLK1 3
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#define GATE_DCLK0 4
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#define GATE_DCLK1 5
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#define MUX_CLKOUT0 6
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#define MUX_CLKOUT1 7
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#define DCLK_MAX_CLKS (MUX_CLKOUT1 + 1)
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enum supported_socs {
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S3C2410,
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S3C2412,
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S3C2440,
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S3C2443,
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};
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struct s3c24xx_dclk_drv_data {
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const char **clkout0_parent_names;
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int clkout0_num_parents;
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const char **clkout1_parent_names;
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int clkout1_num_parents;
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const char **mux_parent_names;
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int mux_num_parents;
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};
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/*
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* Clock for output-parent selection in misccr
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*/
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struct s3c24xx_clkout {
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struct clk_hw hw;
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u32 mask;
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u8 shift;
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unsigned int (*modify_misccr)(unsigned int clr, unsigned int chg);
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};
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#define to_s3c24xx_clkout(_hw) container_of(_hw, struct s3c24xx_clkout, hw)
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static u8 s3c24xx_clkout_get_parent(struct clk_hw *hw)
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{
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struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
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int num_parents = clk_hw_get_num_parents(hw);
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u32 val;
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val = clkout->modify_misccr(0, 0) >> clkout->shift;
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val >>= clkout->shift;
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val &= clkout->mask;
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if (val >= num_parents)
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return -EINVAL;
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return val;
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}
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static int s3c24xx_clkout_set_parent(struct clk_hw *hw, u8 index)
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{
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struct s3c24xx_clkout *clkout = to_s3c24xx_clkout(hw);
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clkout->modify_misccr((clkout->mask << clkout->shift),
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(index << clkout->shift));
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return 0;
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}
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static const struct clk_ops s3c24xx_clkout_ops = {
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.get_parent = s3c24xx_clkout_get_parent,
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.set_parent = s3c24xx_clkout_set_parent,
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.determine_rate = __clk_mux_determine_rate,
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};
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static struct clk_hw *s3c24xx_register_clkout(struct device *dev,
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const char *name, const char **parent_names, u8 num_parents,
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u8 shift, u32 mask)
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{
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struct s3c2410_clk_platform_data *pdata = dev_get_platdata(dev);
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struct s3c24xx_clkout *clkout;
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struct clk_init_data init;
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int ret;
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if (!pdata)
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return ERR_PTR(-EINVAL);
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/* allocate the clkout */
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clkout = kzalloc(sizeof(*clkout), GFP_KERNEL);
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if (!clkout)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &s3c24xx_clkout_ops;
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init.flags = 0;
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init.parent_names = parent_names;
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init.num_parents = num_parents;
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clkout->shift = shift;
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clkout->mask = mask;
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clkout->hw.init = &init;
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clkout->modify_misccr = pdata->modify_misccr;
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ret = clk_hw_register(dev, &clkout->hw);
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if (ret)
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return ERR_PTR(ret);
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return &clkout->hw;
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}
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/*
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* dclk and clkout init
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*/
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struct s3c24xx_dclk {
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struct device *dev;
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void __iomem *base;
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struct notifier_block dclk0_div_change_nb;
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struct notifier_block dclk1_div_change_nb;
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spinlock_t dclk_lock;
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unsigned long reg_save;
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/* clk_data must be the last entry in the structure */
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struct clk_hw_onecell_data clk_data;
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};
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#define to_s3c24xx_dclk0(x) \
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container_of(x, struct s3c24xx_dclk, dclk0_div_change_nb)
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#define to_s3c24xx_dclk1(x) \
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container_of(x, struct s3c24xx_dclk, dclk1_div_change_nb)
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static const char *dclk_s3c2410_p[] = { "pclk", "uclk" };
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static const char *clkout0_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
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"gate_dclk0" };
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static const char *clkout1_s3c2410_p[] = { "mpll", "upll", "fclk", "hclk", "pclk",
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"gate_dclk1" };
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static const char *clkout0_s3c2412_p[] = { "mpll", "upll", "rtc_clkout",
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"hclk", "pclk", "gate_dclk0" };
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static const char *clkout1_s3c2412_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
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"gate_dclk1" };
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static const char *clkout0_s3c2440_p[] = { "xti", "upll", "fclk", "hclk", "pclk",
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"gate_dclk0" };
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static const char *clkout1_s3c2440_p[] = { "mpll", "upll", "rtc_clkout",
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"hclk", "pclk", "gate_dclk1" };
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static const char *dclk_s3c2443_p[] = { "pclk", "epll" };
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static const char *clkout0_s3c2443_p[] = { "xti", "epll", "armclk", "hclk", "pclk",
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"gate_dclk0" };
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static const char *clkout1_s3c2443_p[] = { "dummy", "epll", "rtc_clkout",
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"hclk", "pclk", "gate_dclk1" };
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#define DCLKCON_DCLK_DIV_MASK 0xf
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#define DCLKCON_DCLK0_DIV_SHIFT 4
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#define DCLKCON_DCLK0_CMP_SHIFT 8
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#define DCLKCON_DCLK1_DIV_SHIFT 20
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#define DCLKCON_DCLK1_CMP_SHIFT 24
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static void s3c24xx_dclk_update_cmp(struct s3c24xx_dclk *s3c24xx_dclk,
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int div_shift, int cmp_shift)
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{
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unsigned long flags = 0;
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u32 dclk_con, div, cmp;
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spin_lock_irqsave(&s3c24xx_dclk->dclk_lock, flags);
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dclk_con = readl_relaxed(s3c24xx_dclk->base);
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div = ((dclk_con >> div_shift) & DCLKCON_DCLK_DIV_MASK) + 1;
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cmp = ((div + 1) / 2) - 1;
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dclk_con &= ~(DCLKCON_DCLK_DIV_MASK << cmp_shift);
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dclk_con |= (cmp << cmp_shift);
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writel_relaxed(dclk_con, s3c24xx_dclk->base);
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spin_unlock_irqrestore(&s3c24xx_dclk->dclk_lock, flags);
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}
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static int s3c24xx_dclk0_div_notify(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk0(nb);
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if (event == POST_RATE_CHANGE) {
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s3c24xx_dclk_update_cmp(s3c24xx_dclk,
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DCLKCON_DCLK0_DIV_SHIFT, DCLKCON_DCLK0_CMP_SHIFT);
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}
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return NOTIFY_DONE;
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}
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static int s3c24xx_dclk1_div_notify(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct s3c24xx_dclk *s3c24xx_dclk = to_s3c24xx_dclk1(nb);
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if (event == POST_RATE_CHANGE) {
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s3c24xx_dclk_update_cmp(s3c24xx_dclk,
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DCLKCON_DCLK1_DIV_SHIFT, DCLKCON_DCLK1_CMP_SHIFT);
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}
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return NOTIFY_DONE;
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}
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#ifdef CONFIG_PM_SLEEP
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static int s3c24xx_dclk_suspend(struct device *dev)
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{
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struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
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s3c24xx_dclk->reg_save = readl_relaxed(s3c24xx_dclk->base);
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return 0;
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}
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static int s3c24xx_dclk_resume(struct device *dev)
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{
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struct s3c24xx_dclk *s3c24xx_dclk = dev_get_drvdata(dev);
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writel_relaxed(s3c24xx_dclk->reg_save, s3c24xx_dclk->base);
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return 0;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(s3c24xx_dclk_pm_ops,
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s3c24xx_dclk_suspend, s3c24xx_dclk_resume);
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static int s3c24xx_dclk_probe(struct platform_device *pdev)
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{
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struct s3c24xx_dclk *s3c24xx_dclk;
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struct s3c24xx_dclk_drv_data *dclk_variant;
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struct clk_hw **clk_table;
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int ret, i;
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s3c24xx_dclk = devm_kzalloc(&pdev->dev,
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struct_size(s3c24xx_dclk, clk_data.hws,
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DCLK_MAX_CLKS),
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GFP_KERNEL);
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if (!s3c24xx_dclk)
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return -ENOMEM;
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clk_table = s3c24xx_dclk->clk_data.hws;
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s3c24xx_dclk->dev = &pdev->dev;
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s3c24xx_dclk->clk_data.num = DCLK_MAX_CLKS;
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platform_set_drvdata(pdev, s3c24xx_dclk);
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spin_lock_init(&s3c24xx_dclk->dclk_lock);
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s3c24xx_dclk->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(s3c24xx_dclk->base))
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return PTR_ERR(s3c24xx_dclk->base);
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dclk_variant = (struct s3c24xx_dclk_drv_data *)
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platform_get_device_id(pdev)->driver_data;
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clk_table[MUX_DCLK0] = clk_hw_register_mux(&pdev->dev, "mux_dclk0",
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dclk_variant->mux_parent_names,
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dclk_variant->mux_num_parents, 0,
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s3c24xx_dclk->base, 1, 1, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[MUX_DCLK1] = clk_hw_register_mux(&pdev->dev, "mux_dclk1",
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dclk_variant->mux_parent_names,
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dclk_variant->mux_num_parents, 0,
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s3c24xx_dclk->base, 17, 1, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[DIV_DCLK0] = clk_hw_register_divider(&pdev->dev, "div_dclk0",
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"mux_dclk0", 0, s3c24xx_dclk->base,
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4, 4, 0, &s3c24xx_dclk->dclk_lock);
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clk_table[DIV_DCLK1] = clk_hw_register_divider(&pdev->dev, "div_dclk1",
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"mux_dclk1", 0, s3c24xx_dclk->base,
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20, 4, 0, &s3c24xx_dclk->dclk_lock);
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clk_table[GATE_DCLK0] = clk_hw_register_gate(&pdev->dev, "gate_dclk0",
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"div_dclk0", CLK_SET_RATE_PARENT,
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s3c24xx_dclk->base, 0, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[GATE_DCLK1] = clk_hw_register_gate(&pdev->dev, "gate_dclk1",
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"div_dclk1", CLK_SET_RATE_PARENT,
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s3c24xx_dclk->base, 16, 0,
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&s3c24xx_dclk->dclk_lock);
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clk_table[MUX_CLKOUT0] = s3c24xx_register_clkout(&pdev->dev,
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"clkout0", dclk_variant->clkout0_parent_names,
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dclk_variant->clkout0_num_parents, 4, 7);
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clk_table[MUX_CLKOUT1] = s3c24xx_register_clkout(&pdev->dev,
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"clkout1", dclk_variant->clkout1_parent_names,
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dclk_variant->clkout1_num_parents, 8, 7);
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for (i = 0; i < DCLK_MAX_CLKS; i++)
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if (IS_ERR(clk_table[i])) {
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dev_err(&pdev->dev, "clock %d failed to register\n", i);
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ret = PTR_ERR(clk_table[i]);
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goto err_clk_register;
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}
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ret = clk_hw_register_clkdev(clk_table[MUX_DCLK0], "dclk0", NULL);
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if (!ret)
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ret = clk_hw_register_clkdev(clk_table[MUX_DCLK1], "dclk1",
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NULL);
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if (!ret)
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ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT0],
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"clkout0", NULL);
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if (!ret)
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ret = clk_hw_register_clkdev(clk_table[MUX_CLKOUT1],
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"clkout1", NULL);
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if (ret) {
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dev_err(&pdev->dev, "failed to register aliases, %d\n", ret);
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goto err_clk_register;
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}
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s3c24xx_dclk->dclk0_div_change_nb.notifier_call =
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s3c24xx_dclk0_div_notify;
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s3c24xx_dclk->dclk1_div_change_nb.notifier_call =
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s3c24xx_dclk1_div_notify;
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ret = clk_notifier_register(clk_table[DIV_DCLK0]->clk,
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&s3c24xx_dclk->dclk0_div_change_nb);
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if (ret)
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goto err_clk_register;
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ret = clk_notifier_register(clk_table[DIV_DCLK1]->clk,
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&s3c24xx_dclk->dclk1_div_change_nb);
|
||||
if (ret)
|
||||
goto err_dclk_notify;
|
||||
|
||||
return 0;
|
||||
|
||||
err_dclk_notify:
|
||||
clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
|
||||
&s3c24xx_dclk->dclk0_div_change_nb);
|
||||
err_clk_register:
|
||||
for (i = 0; i < DCLK_MAX_CLKS; i++)
|
||||
if (clk_table[i] && !IS_ERR(clk_table[i]))
|
||||
clk_hw_unregister(clk_table[i]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int s3c24xx_dclk_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct s3c24xx_dclk *s3c24xx_dclk = platform_get_drvdata(pdev);
|
||||
struct clk_hw **clk_table = s3c24xx_dclk->clk_data.hws;
|
||||
int i;
|
||||
|
||||
clk_notifier_unregister(clk_table[DIV_DCLK1]->clk,
|
||||
&s3c24xx_dclk->dclk1_div_change_nb);
|
||||
clk_notifier_unregister(clk_table[DIV_DCLK0]->clk,
|
||||
&s3c24xx_dclk->dclk0_div_change_nb);
|
||||
|
||||
for (i = 0; i < DCLK_MAX_CLKS; i++)
|
||||
clk_hw_unregister(clk_table[i]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct s3c24xx_dclk_drv_data dclk_variants[] = {
|
||||
[S3C2410] = {
|
||||
.clkout0_parent_names = clkout0_s3c2410_p,
|
||||
.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2410_p),
|
||||
.clkout1_parent_names = clkout1_s3c2410_p,
|
||||
.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2410_p),
|
||||
.mux_parent_names = dclk_s3c2410_p,
|
||||
.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
|
||||
},
|
||||
[S3C2412] = {
|
||||
.clkout0_parent_names = clkout0_s3c2412_p,
|
||||
.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2412_p),
|
||||
.clkout1_parent_names = clkout1_s3c2412_p,
|
||||
.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2412_p),
|
||||
.mux_parent_names = dclk_s3c2410_p,
|
||||
.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
|
||||
},
|
||||
[S3C2440] = {
|
||||
.clkout0_parent_names = clkout0_s3c2440_p,
|
||||
.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2440_p),
|
||||
.clkout1_parent_names = clkout1_s3c2440_p,
|
||||
.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2440_p),
|
||||
.mux_parent_names = dclk_s3c2410_p,
|
||||
.mux_num_parents = ARRAY_SIZE(dclk_s3c2410_p),
|
||||
},
|
||||
[S3C2443] = {
|
||||
.clkout0_parent_names = clkout0_s3c2443_p,
|
||||
.clkout0_num_parents = ARRAY_SIZE(clkout0_s3c2443_p),
|
||||
.clkout1_parent_names = clkout1_s3c2443_p,
|
||||
.clkout1_num_parents = ARRAY_SIZE(clkout1_s3c2443_p),
|
||||
.mux_parent_names = dclk_s3c2443_p,
|
||||
.mux_num_parents = ARRAY_SIZE(dclk_s3c2443_p),
|
||||
},
|
||||
};
|
||||
|
||||
static const struct platform_device_id s3c24xx_dclk_driver_ids[] = {
|
||||
{
|
||||
.name = "s3c2410-dclk",
|
||||
.driver_data = (kernel_ulong_t)&dclk_variants[S3C2410],
|
||||
}, {
|
||||
.name = "s3c2412-dclk",
|
||||
.driver_data = (kernel_ulong_t)&dclk_variants[S3C2412],
|
||||
}, {
|
||||
.name = "s3c2440-dclk",
|
||||
.driver_data = (kernel_ulong_t)&dclk_variants[S3C2440],
|
||||
}, {
|
||||
.name = "s3c2443-dclk",
|
||||
.driver_data = (kernel_ulong_t)&dclk_variants[S3C2443],
|
||||
},
|
||||
{ }
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(platform, s3c24xx_dclk_driver_ids);
|
||||
|
||||
static struct platform_driver s3c24xx_dclk_driver = {
|
||||
.driver = {
|
||||
.name = "s3c24xx-dclk",
|
||||
.pm = &s3c24xx_dclk_pm_ops,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = s3c24xx_dclk_probe,
|
||||
.remove = s3c24xx_dclk_remove,
|
||||
.id_table = s3c24xx_dclk_driver_ids,
|
||||
};
|
||||
module_platform_driver(s3c24xx_dclk_driver);
|
||||
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>");
|
||||
MODULE_DESCRIPTION("Driver for the S3C24XX external clock outputs");
|
|
@ -1,446 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* Common Clock Framework support for S3C2410 and following SoCs.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/samsung.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include <dt-bindings/clock/s3c2410.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
#define LOCKTIME 0x00
|
||||
#define MPLLCON 0x04
|
||||
#define UPLLCON 0x08
|
||||
#define CLKCON 0x0c
|
||||
#define CLKSLOW 0x10
|
||||
#define CLKDIVN 0x14
|
||||
#define CAMDIVN 0x18
|
||||
|
||||
/* the soc types */
|
||||
enum supported_socs {
|
||||
S3C2410,
|
||||
S3C2440,
|
||||
S3C2442,
|
||||
};
|
||||
|
||||
/* list of PLLs to be registered */
|
||||
enum s3c2410_plls {
|
||||
mpll, upll,
|
||||
};
|
||||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
*/
|
||||
static unsigned long s3c2410_clk_regs[] __initdata = {
|
||||
LOCKTIME,
|
||||
MPLLCON,
|
||||
UPLLCON,
|
||||
CLKCON,
|
||||
CLKSLOW,
|
||||
CLKDIVN,
|
||||
CAMDIVN,
|
||||
};
|
||||
|
||||
PNAME(fclk_p) = { "mpll", "div_slow" };
|
||||
|
||||
static struct samsung_mux_clock s3c2410_common_muxes[] __initdata = {
|
||||
MUX(FCLK, "fclk", fclk_p, CLKSLOW, 4, 1),
|
||||
};
|
||||
|
||||
static struct clk_div_table divslow_d[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 2, .div = 4 },
|
||||
{ .val = 3, .div = 6 },
|
||||
{ .val = 4, .div = 8 },
|
||||
{ .val = 5, .div = 10 },
|
||||
{ .val = 6, .div = 12 },
|
||||
{ .val = 7, .div = 14 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_div_clock s3c2410_common_dividers[] __initdata = {
|
||||
DIV_T(0, "div_slow", "xti", CLKSLOW, 0, 3, divslow_d),
|
||||
DIV(PCLK, "pclk", "hclk", CLKDIVN, 0, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c2410_common_gates[] __initdata = {
|
||||
GATE(PCLK_SPI, "spi", "pclk", CLKCON, 18, 0, 0),
|
||||
GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 17, 0, 0),
|
||||
GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 16, 0, 0),
|
||||
GATE(PCLK_ADC, "adc", "pclk", CLKCON, 15, 0, 0),
|
||||
GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 14, 0, 0),
|
||||
GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 13, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 12, 0, 0),
|
||||
GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 11, 0, 0),
|
||||
GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 10, 0, 0),
|
||||
GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 9, 0, 0),
|
||||
GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 8, 0, 0),
|
||||
GATE(HCLK_USBD, "usb-device", "hclk", CLKCON, 7, 0, 0),
|
||||
GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
|
||||
GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
|
||||
GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
|
||||
};
|
||||
|
||||
/* should be added _after_ the soc-specific clocks are created */
|
||||
static struct samsung_clock_alias s3c2410_common_aliases[] __initdata = {
|
||||
ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
|
||||
ALIAS(PCLK_ADC, NULL, "adc"),
|
||||
ALIAS(PCLK_RTC, NULL, "rtc"),
|
||||
ALIAS(PCLK_PWM, NULL, "timers"),
|
||||
ALIAS(HCLK_LCD, NULL, "lcd"),
|
||||
ALIAS(HCLK_USBD, NULL, "usb-device"),
|
||||
ALIAS(HCLK_USBH, NULL, "usb-host"),
|
||||
ALIAS(UCLK, NULL, "usb-bus-host"),
|
||||
ALIAS(UCLK, NULL, "usb-bus-gadget"),
|
||||
ALIAS(ARMCLK, NULL, "armclk"),
|
||||
ALIAS(UCLK, NULL, "uclk"),
|
||||
ALIAS(HCLK, NULL, "hclk"),
|
||||
ALIAS(MPLL, NULL, "mpll"),
|
||||
ALIAS(FCLK, NULL, "fclk"),
|
||||
ALIAS(PCLK, NULL, "watchdog"),
|
||||
ALIAS(PCLK_SDI, NULL, "sdi"),
|
||||
ALIAS(HCLK_NAND, NULL, "nand"),
|
||||
ALIAS(PCLK_I2S, NULL, "iis"),
|
||||
ALIAS(PCLK_I2C, NULL, "i2c"),
|
||||
};
|
||||
|
||||
/* S3C2410 specific clocks */
|
||||
|
||||
static struct samsung_pll_rate_table pll_s3c2410_12mhz_tbl[] __initdata = {
|
||||
/* sorted in descending order */
|
||||
/* 2410A extras */
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 270000000, 127, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 268000000, 126, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 266000000, 125, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 226000000, 105, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 210000000, 132, 2, 1),
|
||||
/* 2410 common */
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 202800000, 161, 3, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 192000000, 88, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 186000000, 85, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 180000000, 82, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 170000000, 77, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 158000000, 71, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 152000000, 68, 1, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 147000000, 90, 2, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 135000000, 82, 2, 1),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 124000000, 116, 1, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 118500000, 150, 2, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 113000000, 105, 1, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 101250000, 127, 2, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 90000000, 112, 2, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 84750000, 105, 2, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 79000000, 71, 1, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 67500000, 82, 2, 2),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 56250000, 142, 2, 3),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 48000000, 120, 2, 3),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 50700000, 161, 3, 3),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 45000000, 82, 1, 3),
|
||||
PLL_S3C2410_MPLL_RATE(12 * MHZ, 33750000, 82, 2, 3),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock s3c2410_plls[] __initdata = {
|
||||
[mpll] = PLL(pll_s3c2410_mpll, MPLL, "mpll", "xti",
|
||||
LOCKTIME, MPLLCON, NULL),
|
||||
[upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
|
||||
LOCKTIME, UPLLCON, NULL),
|
||||
};
|
||||
|
||||
static struct samsung_div_clock s3c2410_dividers[] __initdata = {
|
||||
DIV(HCLK, "hclk", "mpll", CLKDIVN, 1, 1),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock s3c2410_ffactor[] __initdata = {
|
||||
/*
|
||||
* armclk is directly supplied by the fclk, without
|
||||
* switching possibility like on the s3c244x below.
|
||||
*/
|
||||
FFACTOR(ARMCLK, "armclk", "fclk", 1, 1, 0),
|
||||
|
||||
/* uclk is fed from the unmodified upll */
|
||||
FFACTOR(UCLK, "uclk", "upll", 1, 1, 0),
|
||||
};
|
||||
|
||||
static struct samsung_clock_alias s3c2410_aliases[] __initdata = {
|
||||
ALIAS(PCLK_UART0, "s3c2410-uart.0", "uart"),
|
||||
ALIAS(PCLK_UART1, "s3c2410-uart.1", "uart"),
|
||||
ALIAS(PCLK_UART2, "s3c2410-uart.2", "uart"),
|
||||
ALIAS(PCLK_UART0, "s3c2410-uart.0", "clk_uart_baud0"),
|
||||
ALIAS(PCLK_UART1, "s3c2410-uart.1", "clk_uart_baud0"),
|
||||
ALIAS(PCLK_UART2, "s3c2410-uart.2", "clk_uart_baud0"),
|
||||
ALIAS(UCLK, NULL, "clk_uart_baud1"),
|
||||
};
|
||||
|
||||
/* S3C244x specific clocks */
|
||||
|
||||
static struct samsung_pll_rate_table pll_s3c244x_12mhz_tbl[] __initdata = {
|
||||
/* sorted in descending order */
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 400000000, 0x5c, 1, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 390000000, 0x7a, 2, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 380000000, 0x57, 1, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 370000000, 0xb1, 4, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 360000000, 0x70, 2, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 350000000, 0xa7, 4, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 340000000, 0x4d, 1, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 330000000, 0x66, 2, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 320000000, 0x98, 4, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 310000000, 0x93, 4, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 300000000, 0x75, 3, 1),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 240000000, 0x70, 1, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 230000000, 0x6b, 1, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 220000000, 0x66, 1, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 210000000, 0x84, 2, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 200000000, 0x5c, 1, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 190000000, 0x57, 1, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 180000000, 0x70, 2, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 170000000, 0x4d, 1, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 160000000, 0x98, 4, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 150000000, 0x75, 3, 2),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 120000000, 0x70, 1, 3),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 110000000, 0x66, 1, 3),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 100000000, 0x5c, 1, 3),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 90000000, 0x70, 2, 3),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 80000000, 0x98, 4, 3),
|
||||
PLL_S3C2440_MPLL_RATE(12 * MHZ, 75000000, 0x75, 3, 3),
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock s3c244x_common_plls[] __initdata = {
|
||||
[mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
|
||||
LOCKTIME, MPLLCON, NULL),
|
||||
[upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "xti",
|
||||
LOCKTIME, UPLLCON, NULL),
|
||||
};
|
||||
|
||||
PNAME(hclk_p) = { "fclk", "div_hclk_2", "div_hclk_4", "div_hclk_3" };
|
||||
PNAME(armclk_p) = { "fclk", "hclk" };
|
||||
|
||||
static struct samsung_mux_clock s3c244x_common_muxes[] __initdata = {
|
||||
MUX(HCLK, "hclk", hclk_p, CLKDIVN, 1, 2),
|
||||
MUX(ARMCLK, "armclk", armclk_p, CAMDIVN, 12, 1),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock s3c244x_common_ffactor[] __initdata = {
|
||||
FFACTOR(0, "div_hclk_2", "fclk", 1, 2, 0),
|
||||
FFACTOR(0, "ff_cam", "div_cam", 2, 1, CLK_SET_RATE_PARENT),
|
||||
};
|
||||
|
||||
static struct clk_div_table div_hclk_4_d[] = {
|
||||
{ .val = 0, .div = 4 },
|
||||
{ .val = 1, .div = 8 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct clk_div_table div_hclk_3_d[] = {
|
||||
{ .val = 0, .div = 3 },
|
||||
{ .val = 1, .div = 6 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_div_clock s3c244x_common_dividers[] __initdata = {
|
||||
DIV(UCLK, "uclk", "upll", CLKDIVN, 3, 1),
|
||||
DIV(0, "div_hclk", "fclk", CLKDIVN, 1, 1),
|
||||
DIV_T(0, "div_hclk_4", "fclk", CAMDIVN, 9, 1, div_hclk_4_d),
|
||||
DIV_T(0, "div_hclk_3", "fclk", CAMDIVN, 8, 1, div_hclk_3_d),
|
||||
DIV(0, "div_cam", "upll", CAMDIVN, 0, 3),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c244x_common_gates[] __initdata = {
|
||||
GATE(HCLK_CAM, "cam", "hclk", CLKCON, 19, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_clock_alias s3c244x_common_aliases[] __initdata = {
|
||||
ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
|
||||
ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
|
||||
ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
|
||||
ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
|
||||
ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
|
||||
ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
|
||||
ALIAS(HCLK_CAM, NULL, "camif"),
|
||||
ALIAS(CAMIF, NULL, "camif-upll"),
|
||||
};
|
||||
|
||||
/* S3C2440 specific clocks */
|
||||
|
||||
PNAME(s3c2440_camif_p) = { "upll", "ff_cam" };
|
||||
|
||||
static struct samsung_mux_clock s3c2440_muxes[] __initdata = {
|
||||
MUX(CAMIF, "camif", s3c2440_camif_p, CAMDIVN, 4, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c2440_gates[] __initdata = {
|
||||
GATE(PCLK_AC97, "ac97", "pclk", CLKCON, 20, 0, 0),
|
||||
};
|
||||
|
||||
/* S3C2442 specific clocks */
|
||||
|
||||
static struct samsung_fixed_factor_clock s3c2442_ffactor[] __initdata = {
|
||||
FFACTOR(0, "upll_3", "upll", 1, 3, 0),
|
||||
};
|
||||
|
||||
PNAME(s3c2442_camif_p) = { "upll", "ff_cam", "upll", "upll_3" };
|
||||
|
||||
static struct samsung_mux_clock s3c2442_muxes[] __initdata = {
|
||||
MUX(CAMIF, "camif", s3c2442_camif_p, CAMDIVN, 4, 2),
|
||||
};
|
||||
|
||||
/*
|
||||
* fixed rate clocks generated outside the soc
|
||||
* Only necessary until the devicetree-move is complete
|
||||
*/
|
||||
#define XTI 1
|
||||
static struct samsung_fixed_rate_clock s3c2410_common_frate_clks[] __initdata = {
|
||||
FRATE(XTI, "xti", NULL, 0, 0),
|
||||
};
|
||||
|
||||
static void __init s3c2410_common_clk_register_fixed_ext(
|
||||
struct samsung_clk_provider *ctx,
|
||||
unsigned long xti_f)
|
||||
{
|
||||
struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
|
||||
|
||||
s3c2410_common_frate_clks[0].fixed_rate = xti_f;
|
||||
samsung_clk_register_fixed_rate(ctx, s3c2410_common_frate_clks,
|
||||
ARRAY_SIZE(s3c2410_common_frate_clks));
|
||||
|
||||
samsung_clk_register_alias(ctx, &xti_alias, 1);
|
||||
}
|
||||
|
||||
void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
int current_soc,
|
||||
void __iomem *base)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
struct clk_hw **hws;
|
||||
reg_base = base;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
}
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
|
||||
hws = ctx->clk_data.hws;
|
||||
|
||||
/* Register external clocks only in non-dt cases */
|
||||
if (!np)
|
||||
s3c2410_common_clk_register_fixed_ext(ctx, xti_f);
|
||||
|
||||
if (current_soc == S3C2410) {
|
||||
if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
|
||||
s3c2410_plls[mpll].rate_table = pll_s3c2410_12mhz_tbl;
|
||||
s3c2410_plls[upll].rate_table = pll_s3c2410_12mhz_tbl;
|
||||
}
|
||||
|
||||
/* Register PLLs. */
|
||||
samsung_clk_register_pll(ctx, s3c2410_plls,
|
||||
ARRAY_SIZE(s3c2410_plls), reg_base);
|
||||
|
||||
} else { /* S3C2440, S3C2442 */
|
||||
if (clk_hw_get_rate(hws[XTI]) == 12 * MHZ) {
|
||||
/*
|
||||
* plls follow different calculation schemes, with the
|
||||
* upll following the same scheme as the s3c2410 plls
|
||||
*/
|
||||
s3c244x_common_plls[mpll].rate_table =
|
||||
pll_s3c244x_12mhz_tbl;
|
||||
s3c244x_common_plls[upll].rate_table =
|
||||
pll_s3c2410_12mhz_tbl;
|
||||
}
|
||||
|
||||
/* Register PLLs. */
|
||||
samsung_clk_register_pll(ctx, s3c244x_common_plls,
|
||||
ARRAY_SIZE(s3c244x_common_plls), reg_base);
|
||||
}
|
||||
|
||||
/* Register common internal clocks. */
|
||||
samsung_clk_register_mux(ctx, s3c2410_common_muxes,
|
||||
ARRAY_SIZE(s3c2410_common_muxes));
|
||||
samsung_clk_register_div(ctx, s3c2410_common_dividers,
|
||||
ARRAY_SIZE(s3c2410_common_dividers));
|
||||
samsung_clk_register_gate(ctx, s3c2410_common_gates,
|
||||
ARRAY_SIZE(s3c2410_common_gates));
|
||||
|
||||
if (current_soc == S3C2440 || current_soc == S3C2442) {
|
||||
samsung_clk_register_div(ctx, s3c244x_common_dividers,
|
||||
ARRAY_SIZE(s3c244x_common_dividers));
|
||||
samsung_clk_register_gate(ctx, s3c244x_common_gates,
|
||||
ARRAY_SIZE(s3c244x_common_gates));
|
||||
samsung_clk_register_mux(ctx, s3c244x_common_muxes,
|
||||
ARRAY_SIZE(s3c244x_common_muxes));
|
||||
samsung_clk_register_fixed_factor(ctx, s3c244x_common_ffactor,
|
||||
ARRAY_SIZE(s3c244x_common_ffactor));
|
||||
}
|
||||
|
||||
/* Register SoC-specific clocks. */
|
||||
switch (current_soc) {
|
||||
case S3C2410:
|
||||
samsung_clk_register_div(ctx, s3c2410_dividers,
|
||||
ARRAY_SIZE(s3c2410_dividers));
|
||||
samsung_clk_register_fixed_factor(ctx, s3c2410_ffactor,
|
||||
ARRAY_SIZE(s3c2410_ffactor));
|
||||
samsung_clk_register_alias(ctx, s3c2410_aliases,
|
||||
ARRAY_SIZE(s3c2410_aliases));
|
||||
break;
|
||||
case S3C2440:
|
||||
samsung_clk_register_mux(ctx, s3c2440_muxes,
|
||||
ARRAY_SIZE(s3c2440_muxes));
|
||||
samsung_clk_register_gate(ctx, s3c2440_gates,
|
||||
ARRAY_SIZE(s3c2440_gates));
|
||||
break;
|
||||
case S3C2442:
|
||||
samsung_clk_register_mux(ctx, s3c2442_muxes,
|
||||
ARRAY_SIZE(s3c2442_muxes));
|
||||
samsung_clk_register_fixed_factor(ctx, s3c2442_ffactor,
|
||||
ARRAY_SIZE(s3c2442_ffactor));
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Register common aliases at the end, as some of the aliased clocks
|
||||
* are SoC specific.
|
||||
*/
|
||||
samsung_clk_register_alias(ctx, s3c2410_common_aliases,
|
||||
ARRAY_SIZE(s3c2410_common_aliases));
|
||||
|
||||
if (current_soc == S3C2440 || current_soc == S3C2442) {
|
||||
samsung_clk_register_alias(ctx, s3c244x_common_aliases,
|
||||
ARRAY_SIZE(s3c244x_common_aliases));
|
||||
}
|
||||
|
||||
samsung_clk_sleep_init(reg_base, s3c2410_clk_regs,
|
||||
ARRAY_SIZE(s3c2410_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
}
|
||||
|
||||
static void __init s3c2410_clk_init(struct device_node *np)
|
||||
{
|
||||
s3c2410_common_clk_init(np, 0, S3C2410, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(s3c2410_clk, "samsung,s3c2410-clock", s3c2410_clk_init);
|
||||
|
||||
static void __init s3c2440_clk_init(struct device_node *np)
|
||||
{
|
||||
s3c2410_common_clk_init(np, 0, S3C2440, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(s3c2440_clk, "samsung,s3c2440-clock", s3c2440_clk_init);
|
||||
|
||||
static void __init s3c2442_clk_init(struct device_node *np)
|
||||
{
|
||||
s3c2410_common_clk_init(np, 0, S3C2442, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(s3c2442_clk, "samsung,s3c2442-clock", s3c2442_clk_init);
|
|
@ -1,254 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* Common Clock Framework support for S3C2412 and S3C2413.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/samsung.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <dt-bindings/clock/s3c2412.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
#define LOCKTIME 0x00
|
||||
#define MPLLCON 0x04
|
||||
#define UPLLCON 0x08
|
||||
#define CLKCON 0x0c
|
||||
#define CLKDIVN 0x14
|
||||
#define CLKSRC 0x1c
|
||||
#define SWRST 0x30
|
||||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
*/
|
||||
static unsigned long s3c2412_clk_regs[] __initdata = {
|
||||
LOCKTIME,
|
||||
MPLLCON,
|
||||
UPLLCON,
|
||||
CLKCON,
|
||||
CLKDIVN,
|
||||
CLKSRC,
|
||||
};
|
||||
|
||||
static struct clk_div_table divxti_d[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 2, .div = 4 },
|
||||
{ .val = 3, .div = 6 },
|
||||
{ .val = 4, .div = 8 },
|
||||
{ .val = 5, .div = 10 },
|
||||
{ .val = 6, .div = 12 },
|
||||
{ .val = 7, .div = 14 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_div_clock s3c2412_dividers[] __initdata = {
|
||||
DIV_T(0, "div_xti", "xti", CLKSRC, 0, 3, divxti_d),
|
||||
DIV(0, "div_cam", "mux_cam", CLKDIVN, 16, 4),
|
||||
DIV(0, "div_i2s", "mux_i2s", CLKDIVN, 12, 4),
|
||||
DIV(0, "div_uart", "mux_uart", CLKDIVN, 8, 4),
|
||||
DIV(0, "div_usb", "mux_usb", CLKDIVN, 6, 1),
|
||||
DIV(0, "div_hclk_half", "hclk", CLKDIVN, 5, 1),
|
||||
DIV(ARMDIV, "armdiv", "msysclk", CLKDIVN, 3, 1),
|
||||
DIV(PCLK, "pclk", "hclk", CLKDIVN, 2, 1),
|
||||
DIV(HCLK, "hclk", "armdiv", CLKDIVN, 0, 2),
|
||||
};
|
||||
|
||||
static struct samsung_fixed_factor_clock s3c2412_ffactor[] __initdata = {
|
||||
FFACTOR(0, "ff_hclk", "hclk", 2, 1, CLK_SET_RATE_PARENT),
|
||||
};
|
||||
|
||||
/*
|
||||
* The first two use the OM[4] setting, which is not readable from
|
||||
* software, so assume it is set to xti.
|
||||
*/
|
||||
PNAME(erefclk_p) = { "xti", "xti", "xti", "ext" };
|
||||
PNAME(urefclk_p) = { "xti", "xti", "xti", "ext" };
|
||||
|
||||
PNAME(camclk_p) = { "usysclk", "hclk" };
|
||||
PNAME(usbclk_p) = { "usysclk", "hclk" };
|
||||
PNAME(i2sclk_p) = { "erefclk", "mpll" };
|
||||
PNAME(uartclk_p) = { "erefclk", "mpll" };
|
||||
PNAME(usysclk_p) = { "urefclk", "upll" };
|
||||
PNAME(msysclk_p) = { "mdivclk", "mpll" };
|
||||
PNAME(mdivclk_p) = { "xti", "div_xti" };
|
||||
PNAME(armclk_p) = { "armdiv", "hclk" };
|
||||
|
||||
static struct samsung_mux_clock s3c2412_muxes[] __initdata = {
|
||||
MUX(0, "erefclk", erefclk_p, CLKSRC, 14, 2),
|
||||
MUX(0, "urefclk", urefclk_p, CLKSRC, 12, 2),
|
||||
MUX(0, "mux_cam", camclk_p, CLKSRC, 11, 1),
|
||||
MUX(0, "mux_usb", usbclk_p, CLKSRC, 10, 1),
|
||||
MUX(0, "mux_i2s", i2sclk_p, CLKSRC, 9, 1),
|
||||
MUX(0, "mux_uart", uartclk_p, CLKSRC, 8, 1),
|
||||
MUX(USYSCLK, "usysclk", usysclk_p, CLKSRC, 5, 1),
|
||||
MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
|
||||
MUX(MDIVCLK, "mdivclk", mdivclk_p, CLKSRC, 3, 1),
|
||||
MUX(ARMCLK, "armclk", armclk_p, CLKDIVN, 4, 1),
|
||||
};
|
||||
|
||||
static struct samsung_pll_clock s3c2412_plls[] __initdata = {
|
||||
PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
|
||||
PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c2412_gates[] __initdata = {
|
||||
GATE(PCLK_WDT, "wdt", "pclk", CLKCON, 28, 0, 0),
|
||||
GATE(PCLK_SPI, "spi", "pclk", CLKCON, 27, 0, 0),
|
||||
GATE(PCLK_I2S, "i2s", "pclk", CLKCON, 26, 0, 0),
|
||||
GATE(PCLK_I2C, "i2c", "pclk", CLKCON, 25, 0, 0),
|
||||
GATE(PCLK_ADC, "adc", "pclk", CLKCON, 24, 0, 0),
|
||||
GATE(PCLK_RTC, "rtc", "pclk", CLKCON, 23, 0, 0),
|
||||
GATE(PCLK_GPIO, "gpio", "pclk", CLKCON, 22, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PCLK_UART2, "uart2", "pclk", CLKCON, 21, 0, 0),
|
||||
GATE(PCLK_UART1, "uart1", "pclk", CLKCON, 20, 0, 0),
|
||||
GATE(PCLK_UART0, "uart0", "pclk", CLKCON, 19, 0, 0),
|
||||
GATE(PCLK_SDI, "sdi", "pclk", CLKCON, 18, 0, 0),
|
||||
GATE(PCLK_PWM, "pwm", "pclk", CLKCON, 17, 0, 0),
|
||||
GATE(PCLK_USBD, "usb-device", "pclk", CLKCON, 16, 0, 0),
|
||||
GATE(SCLK_CAM, "sclk_cam", "div_cam", CLKCON, 15, 0, 0),
|
||||
GATE(SCLK_UART, "sclk_uart", "div_uart", CLKCON, 14, 0, 0),
|
||||
GATE(SCLK_I2S, "sclk_i2s", "div_i2s", CLKCON, 13, 0, 0),
|
||||
GATE(SCLK_USBH, "sclk_usbh", "div_usb", CLKCON, 12, 0, 0),
|
||||
GATE(SCLK_USBD, "sclk_usbd", "div_usb", CLKCON, 11, 0, 0),
|
||||
GATE(HCLK_HALF, "hclk_half", "div_hclk_half", CLKCON, 10, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_X2, "hclkx2", "ff_hclk", CLKCON, 9, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_SDRAM, "sdram", "hclk", CLKCON, 8, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_USBH, "usb-host", "hclk", CLKCON, 6, 0, 0),
|
||||
GATE(HCLK_LCD, "lcd", "hclk", CLKCON, 5, 0, 0),
|
||||
GATE(HCLK_NAND, "nand", "hclk", CLKCON, 4, 0, 0),
|
||||
GATE(HCLK_DMA3, "dma3", "hclk", CLKCON, 3, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA2, "dma2", "hclk", CLKCON, 2, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA1, "dma1", "hclk", CLKCON, 1, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA0, "dma0", "hclk", CLKCON, 0, CLK_IGNORE_UNUSED, 0),
|
||||
};
|
||||
|
||||
static struct samsung_clock_alias s3c2412_aliases[] __initdata = {
|
||||
ALIAS(PCLK_UART0, "s3c2412-uart.0", "uart"),
|
||||
ALIAS(PCLK_UART1, "s3c2412-uart.1", "uart"),
|
||||
ALIAS(PCLK_UART2, "s3c2412-uart.2", "uart"),
|
||||
ALIAS(PCLK_UART0, "s3c2412-uart.0", "clk_uart_baud2"),
|
||||
ALIAS(PCLK_UART1, "s3c2412-uart.1", "clk_uart_baud2"),
|
||||
ALIAS(PCLK_UART2, "s3c2412-uart.2", "clk_uart_baud2"),
|
||||
ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
|
||||
ALIAS(PCLK_I2C, "s3c2410-i2c.0", "i2c"),
|
||||
ALIAS(PCLK_ADC, NULL, "adc"),
|
||||
ALIAS(PCLK_RTC, NULL, "rtc"),
|
||||
ALIAS(PCLK_PWM, NULL, "timers"),
|
||||
ALIAS(HCLK_LCD, NULL, "lcd"),
|
||||
ALIAS(PCLK_USBD, NULL, "usb-device"),
|
||||
ALIAS(SCLK_USBD, NULL, "usb-bus-gadget"),
|
||||
ALIAS(HCLK_USBH, NULL, "usb-host"),
|
||||
ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
|
||||
ALIAS(ARMCLK, NULL, "armclk"),
|
||||
ALIAS(HCLK, NULL, "hclk"),
|
||||
ALIAS(MPLL, NULL, "mpll"),
|
||||
ALIAS(MSYSCLK, NULL, "fclk"),
|
||||
};
|
||||
|
||||
static int s3c2412_restart(struct notifier_block *this,
|
||||
unsigned long mode, void *cmd)
|
||||
{
|
||||
/* errata "Watch-dog/Software Reset Problem" specifies that
|
||||
* this reset must be done with the SYSCLK sourced from
|
||||
* EXTCLK instead of FOUT to avoid a glitch in the reset
|
||||
* mechanism.
|
||||
*
|
||||
* See the watchdog section of the S3C2412 manual for more
|
||||
* information on this fix.
|
||||
*/
|
||||
|
||||
__raw_writel(0x00, reg_base + CLKSRC);
|
||||
__raw_writel(0x533C2412, reg_base + SWRST);
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block s3c2412_restart_handler = {
|
||||
.notifier_call = s3c2412_restart,
|
||||
.priority = 129,
|
||||
};
|
||||
|
||||
/*
|
||||
* fixed rate clocks generated outside the soc
|
||||
* Only necessary until the devicetree-move is complete
|
||||
*/
|
||||
#define XTI 1
|
||||
static struct samsung_fixed_rate_clock s3c2412_common_frate_clks[] __initdata = {
|
||||
FRATE(XTI, "xti", NULL, 0, 0),
|
||||
FRATE(0, "ext", NULL, 0, 0),
|
||||
};
|
||||
|
||||
static void __init s3c2412_common_clk_register_fixed_ext(
|
||||
struct samsung_clk_provider *ctx,
|
||||
unsigned long xti_f, unsigned long ext_f)
|
||||
{
|
||||
/* xtal alias is necessary for the current cpufreq driver */
|
||||
struct samsung_clock_alias xti_alias = ALIAS(XTI, NULL, "xtal");
|
||||
|
||||
s3c2412_common_frate_clks[0].fixed_rate = xti_f;
|
||||
s3c2412_common_frate_clks[1].fixed_rate = ext_f;
|
||||
samsung_clk_register_fixed_rate(ctx, s3c2412_common_frate_clks,
|
||||
ARRAY_SIZE(s3c2412_common_frate_clks));
|
||||
|
||||
samsung_clk_register_alias(ctx, &xti_alias, 1);
|
||||
}
|
||||
|
||||
void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
unsigned long ext_f, void __iomem *base)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
int ret;
|
||||
reg_base = base;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
}
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
|
||||
|
||||
/* Register external clocks only in non-dt cases */
|
||||
if (!np)
|
||||
s3c2412_common_clk_register_fixed_ext(ctx, xti_f, ext_f);
|
||||
|
||||
/* Register PLLs. */
|
||||
samsung_clk_register_pll(ctx, s3c2412_plls, ARRAY_SIZE(s3c2412_plls),
|
||||
reg_base);
|
||||
|
||||
/* Register common internal clocks. */
|
||||
samsung_clk_register_mux(ctx, s3c2412_muxes, ARRAY_SIZE(s3c2412_muxes));
|
||||
samsung_clk_register_div(ctx, s3c2412_dividers,
|
||||
ARRAY_SIZE(s3c2412_dividers));
|
||||
samsung_clk_register_gate(ctx, s3c2412_gates,
|
||||
ARRAY_SIZE(s3c2412_gates));
|
||||
samsung_clk_register_fixed_factor(ctx, s3c2412_ffactor,
|
||||
ARRAY_SIZE(s3c2412_ffactor));
|
||||
samsung_clk_register_alias(ctx, s3c2412_aliases,
|
||||
ARRAY_SIZE(s3c2412_aliases));
|
||||
|
||||
samsung_clk_sleep_init(reg_base, s3c2412_clk_regs,
|
||||
ARRAY_SIZE(s3c2412_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
ret = register_restart_handler(&s3c2412_restart_handler);
|
||||
if (ret)
|
||||
pr_warn("cannot register restart handler, %d\n", ret);
|
||||
}
|
||||
|
||||
static void __init s3c2412_clk_init(struct device_node *np)
|
||||
{
|
||||
s3c2412_common_clk_init(np, 0, 0, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(s3c2412_clk, "samsung,s3c2412-clock", s3c2412_clk_init);
|
|
@ -1,438 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
|
||||
*
|
||||
* Common Clock Framework support for S3C2443 and following SoCs.
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/samsung.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/reboot.h>
|
||||
|
||||
#include <dt-bindings/clock/s3c2443.h>
|
||||
|
||||
#include "clk.h"
|
||||
#include "clk-pll.h"
|
||||
|
||||
/* S3C2416 clock controller register offsets */
|
||||
#define LOCKCON0 0x00
|
||||
#define LOCKCON1 0x04
|
||||
#define MPLLCON 0x10
|
||||
#define EPLLCON 0x18
|
||||
#define EPLLCON_K 0x1C
|
||||
#define CLKSRC 0x20
|
||||
#define CLKDIV0 0x24
|
||||
#define CLKDIV1 0x28
|
||||
#define CLKDIV2 0x2C
|
||||
#define HCLKCON 0x30
|
||||
#define PCLKCON 0x34
|
||||
#define SCLKCON 0x38
|
||||
#define SWRST 0x44
|
||||
|
||||
/* the soc types */
|
||||
enum supported_socs {
|
||||
S3C2416,
|
||||
S3C2443,
|
||||
S3C2450,
|
||||
};
|
||||
|
||||
static void __iomem *reg_base;
|
||||
|
||||
/*
|
||||
* list of controller registers to be saved and restored during a
|
||||
* suspend/resume cycle.
|
||||
*/
|
||||
static unsigned long s3c2443_clk_regs[] __initdata = {
|
||||
LOCKCON0,
|
||||
LOCKCON1,
|
||||
MPLLCON,
|
||||
EPLLCON,
|
||||
EPLLCON_K,
|
||||
CLKSRC,
|
||||
CLKDIV0,
|
||||
CLKDIV1,
|
||||
CLKDIV2,
|
||||
PCLKCON,
|
||||
HCLKCON,
|
||||
SCLKCON,
|
||||
};
|
||||
|
||||
PNAME(epllref_p) = { "mpllref", "mpllref", "xti", "ext" };
|
||||
PNAME(esysclk_p) = { "epllref", "epll" };
|
||||
PNAME(mpllref_p) = { "xti", "mdivclk" };
|
||||
PNAME(msysclk_p) = { "mpllref", "mpll" };
|
||||
PNAME(armclk_p) = { "armdiv" , "hclk" };
|
||||
PNAME(i2s0_p) = { "div_i2s0", "ext_i2s", "epllref", "epllref" };
|
||||
|
||||
static struct samsung_mux_clock s3c2443_common_muxes[] __initdata = {
|
||||
MUX(0, "epllref", epllref_p, CLKSRC, 7, 2),
|
||||
MUX(ESYSCLK, "esysclk", esysclk_p, CLKSRC, 6, 1),
|
||||
MUX(0, "mpllref", mpllref_p, CLKSRC, 3, 1),
|
||||
MUX(MSYSCLK, "msysclk", msysclk_p, CLKSRC, 4, 1),
|
||||
MUX(ARMCLK, "armclk", armclk_p, CLKDIV0, 13, 1),
|
||||
MUX(0, "mux_i2s0", i2s0_p, CLKSRC, 14, 2),
|
||||
};
|
||||
|
||||
static struct clk_div_table hclk_d[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 3, .div = 4 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct clk_div_table mdivclk_d[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 3 },
|
||||
{ .val = 2, .div = 5 },
|
||||
{ .val = 3, .div = 7 },
|
||||
{ .val = 4, .div = 9 },
|
||||
{ .val = 5, .div = 11 },
|
||||
{ .val = 6, .div = 13 },
|
||||
{ .val = 7, .div = 15 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_div_clock s3c2443_common_dividers[] __initdata = {
|
||||
DIV_T(0, "mdivclk", "xti", CLKDIV0, 6, 3, mdivclk_d),
|
||||
DIV(0, "prediv", "msysclk", CLKDIV0, 4, 2),
|
||||
DIV_T(HCLK, "hclk", "prediv", CLKDIV0, 0, 2, hclk_d),
|
||||
DIV(PCLK, "pclk", "hclk", CLKDIV0, 2, 1),
|
||||
DIV(0, "div_hsspi0_epll", "esysclk", CLKDIV1, 24, 2),
|
||||
DIV(0, "div_fimd", "esysclk", CLKDIV1, 16, 8),
|
||||
DIV(0, "div_i2s0", "esysclk", CLKDIV1, 12, 4),
|
||||
DIV(0, "div_uart", "esysclk", CLKDIV1, 8, 4),
|
||||
DIV(0, "div_hsmmc1", "esysclk", CLKDIV1, 6, 2),
|
||||
DIV(0, "div_usbhost", "esysclk", CLKDIV1, 4, 2),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c2443_common_gates[] __initdata = {
|
||||
GATE(SCLK_HSMMC_EXT, "sclk_hsmmcext", "ext", SCLKCON, 13, 0, 0),
|
||||
GATE(SCLK_HSMMC1, "sclk_hsmmc1", "div_hsmmc1", SCLKCON, 12, 0, 0),
|
||||
GATE(SCLK_FIMD, "sclk_fimd", "div_fimd", SCLKCON, 10, 0, 0),
|
||||
GATE(SCLK_I2S0, "sclk_i2s0", "mux_i2s0", SCLKCON, 9, 0, 0),
|
||||
GATE(SCLK_UART, "sclk_uart", "div_uart", SCLKCON, 8, 0, 0),
|
||||
GATE(SCLK_USBH, "sclk_usbhost", "div_usbhost", SCLKCON, 1, 0, 0),
|
||||
GATE(HCLK_DRAM, "dram", "hclk", HCLKCON, 19, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_SSMC, "ssmc", "hclk", HCLKCON, 18, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_HSMMC1, "hsmmc1", "hclk", HCLKCON, 16, 0, 0),
|
||||
GATE(HCLK_USBD, "usb-device", "hclk", HCLKCON, 12, 0, 0),
|
||||
GATE(HCLK_USBH, "usb-host", "hclk", HCLKCON, 11, 0, 0),
|
||||
GATE(HCLK_LCD, "lcd", "hclk", HCLKCON, 9, 0, 0),
|
||||
GATE(HCLK_DMA5, "dma5", "hclk", HCLKCON, 5, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA4, "dma4", "hclk", HCLKCON, 4, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA3, "dma3", "hclk", HCLKCON, 3, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA2, "dma2", "hclk", HCLKCON, 2, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA1, "dma1", "hclk", HCLKCON, 1, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA0, "dma0", "hclk", HCLKCON, 0, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PCLK_GPIO, "gpio", "pclk", PCLKCON, 13, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PCLK_RTC, "rtc", "pclk", PCLKCON, 12, 0, 0),
|
||||
GATE(PCLK_WDT, "wdt", "pclk", PCLKCON, 11, 0, 0),
|
||||
GATE(PCLK_PWM, "pwm", "pclk", PCLKCON, 10, 0, 0),
|
||||
GATE(PCLK_I2S0, "i2s0", "pclk", PCLKCON, 9, 0, 0),
|
||||
GATE(PCLK_AC97, "ac97", "pclk", PCLKCON, 8, 0, 0),
|
||||
GATE(PCLK_ADC, "adc", "pclk", PCLKCON, 7, 0, 0),
|
||||
GATE(PCLK_SPI0, "spi0", "pclk", PCLKCON, 6, 0, 0),
|
||||
GATE(PCLK_I2C0, "i2c0", "pclk", PCLKCON, 4, 0, 0),
|
||||
GATE(PCLK_UART3, "uart3", "pclk", PCLKCON, 3, 0, 0),
|
||||
GATE(PCLK_UART2, "uart2", "pclk", PCLKCON, 2, 0, 0),
|
||||
GATE(PCLK_UART1, "uart1", "pclk", PCLKCON, 1, 0, 0),
|
||||
GATE(PCLK_UART0, "uart0", "pclk", PCLKCON, 0, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
|
||||
ALIAS(MSYSCLK, NULL, "msysclk"),
|
||||
ALIAS(ARMCLK, NULL, "armclk"),
|
||||
ALIAS(MPLL, NULL, "mpll"),
|
||||
ALIAS(EPLL, NULL, "epll"),
|
||||
ALIAS(HCLK, NULL, "hclk"),
|
||||
ALIAS(HCLK_SSMC, NULL, "nand"),
|
||||
ALIAS(PCLK_UART0, "s3c2440-uart.0", "uart"),
|
||||
ALIAS(PCLK_UART1, "s3c2440-uart.1", "uart"),
|
||||
ALIAS(PCLK_UART2, "s3c2440-uart.2", "uart"),
|
||||
ALIAS(PCLK_UART3, "s3c2440-uart.3", "uart"),
|
||||
ALIAS(PCLK_UART0, "s3c2440-uart.0", "clk_uart_baud2"),
|
||||
ALIAS(PCLK_UART1, "s3c2440-uart.1", "clk_uart_baud2"),
|
||||
ALIAS(PCLK_UART2, "s3c2440-uart.2", "clk_uart_baud2"),
|
||||
ALIAS(PCLK_UART3, "s3c2440-uart.3", "clk_uart_baud2"),
|
||||
ALIAS(SCLK_UART, NULL, "clk_uart_baud3"),
|
||||
ALIAS(PCLK_PWM, NULL, "timers"),
|
||||
ALIAS(PCLK_RTC, NULL, "rtc"),
|
||||
ALIAS(PCLK_WDT, NULL, "watchdog"),
|
||||
ALIAS(PCLK_ADC, NULL, "adc"),
|
||||
ALIAS(PCLK_I2C0, "s3c2410-i2c.0", "i2c"),
|
||||
ALIAS(HCLK_USBD, NULL, "usb-device"),
|
||||
ALIAS(HCLK_USBH, NULL, "usb-host"),
|
||||
ALIAS(SCLK_USBH, NULL, "usb-bus-host"),
|
||||
ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi"),
|
||||
ALIAS(PCLK_SPI0, "s3c2443-spi.0", "spi_busclk0"),
|
||||
ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "hsmmc"),
|
||||
ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
|
||||
ALIAS(PCLK_I2S0, "samsung-i2s.0", "iis"),
|
||||
ALIAS(SCLK_I2S0, NULL, "i2s-if"),
|
||||
ALIAS(HCLK_LCD, NULL, "lcd"),
|
||||
ALIAS(SCLK_FIMD, NULL, "sclk_fimd"),
|
||||
};
|
||||
|
||||
/* S3C2416 specific clocks */
|
||||
|
||||
static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
|
||||
PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
|
||||
PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
|
||||
};
|
||||
|
||||
PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
|
||||
PNAME(s3c2416_hsmmc1_p) = { "sclk_hsmmc1", "sclk_hsmmcext" };
|
||||
PNAME(s3c2416_hsspi0_p) = { "hsspi0_epll", "hsspi0_mpll" };
|
||||
|
||||
static struct clk_div_table armdiv_s3c2416_d[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 1, .div = 2 },
|
||||
{ .val = 2, .div = 3 },
|
||||
{ .val = 3, .div = 4 },
|
||||
{ .val = 5, .div = 6 },
|
||||
{ .val = 7, .div = 8 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_div_clock s3c2416_dividers[] __initdata = {
|
||||
DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 3, armdiv_s3c2416_d),
|
||||
DIV(0, "div_hsspi0_mpll", "msysclk", CLKDIV2, 0, 4),
|
||||
DIV(0, "div_hsmmc0", "esysclk", CLKDIV2, 6, 2),
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock s3c2416_muxes[] __initdata = {
|
||||
MUX(MUX_HSMMC0, "mux_hsmmc0", s3c2416_hsmmc0_p, CLKSRC, 16, 1),
|
||||
MUX(MUX_HSMMC1, "mux_hsmmc1", s3c2416_hsmmc1_p, CLKSRC, 17, 1),
|
||||
MUX(MUX_HSSPI0, "mux_hsspi0", s3c2416_hsspi0_p, CLKSRC, 18, 1),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c2416_gates[] __initdata = {
|
||||
GATE(0, "hsspi0_mpll", "div_hsspi0_mpll", SCLKCON, 19, 0, 0),
|
||||
GATE(0, "hsspi0_epll", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
|
||||
GATE(0, "sclk_hsmmc0", "div_hsmmc0", SCLKCON, 6, 0, 0),
|
||||
GATE(HCLK_2D, "2d", "hclk", HCLKCON, 20, 0, 0),
|
||||
GATE(HCLK_HSMMC0, "hsmmc0", "hclk", HCLKCON, 15, 0, 0),
|
||||
GATE(HCLK_IROM, "irom", "hclk", HCLKCON, 13, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PCLK_PCM, "pcm", "pclk", PCLKCON, 19, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_clock_alias s3c2416_aliases[] __initdata = {
|
||||
ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
|
||||
ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
|
||||
ALIAS(MUX_HSMMC0, "s3c-sdhci.0", "mmc_busclk.2"),
|
||||
ALIAS(MUX_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
|
||||
ALIAS(MUX_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
|
||||
ALIAS(ARMDIV, NULL, "armdiv"),
|
||||
};
|
||||
|
||||
/* S3C2443 specific clocks */
|
||||
|
||||
static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
|
||||
PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
|
||||
PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
|
||||
};
|
||||
|
||||
static struct clk_div_table armdiv_s3c2443_d[] = {
|
||||
{ .val = 0, .div = 1 },
|
||||
{ .val = 8, .div = 2 },
|
||||
{ .val = 2, .div = 3 },
|
||||
{ .val = 9, .div = 4 },
|
||||
{ .val = 10, .div = 6 },
|
||||
{ .val = 11, .div = 8 },
|
||||
{ .val = 13, .div = 12 },
|
||||
{ .val = 15, .div = 16 },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct samsung_div_clock s3c2443_dividers[] __initdata = {
|
||||
DIV_T(ARMDIV, "armdiv", "msysclk", CLKDIV0, 9, 4, armdiv_s3c2443_d),
|
||||
DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c2443_gates[] __initdata = {
|
||||
GATE(SCLK_HSSPI0, "sclk_hsspi0", "div_hsspi0_epll", SCLKCON, 14, 0, 0),
|
||||
GATE(SCLK_CAM, "sclk_cam", "div_cam", SCLKCON, 11, 0, 0),
|
||||
GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
|
||||
GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 15, 0, 0),
|
||||
GATE(PCLK_SDI, "sdi", "pclk", PCLKCON, 5, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_clock_alias s3c2443_aliases[] __initdata = {
|
||||
ALIAS(SCLK_HSSPI0, "s3c2443-spi.0", "spi_busclk2"),
|
||||
ALIAS(SCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.2"),
|
||||
ALIAS(SCLK_CAM, NULL, "camif-upll"),
|
||||
ALIAS(PCLK_SPI1, "s3c2410-spi.0", "spi"),
|
||||
ALIAS(PCLK_SDI, NULL, "sdi"),
|
||||
ALIAS(HCLK_CFC, NULL, "cfc"),
|
||||
ALIAS(ARMDIV, NULL, "armdiv"),
|
||||
};
|
||||
|
||||
/* S3C2450 specific clocks */
|
||||
|
||||
PNAME(s3c2450_cam_p) = { "div_cam", "hclk" };
|
||||
PNAME(s3c2450_hsspi1_p) = { "hsspi1_epll", "hsspi1_mpll" };
|
||||
PNAME(i2s1_p) = { "div_i2s1", "ext_i2s", "epllref", "epllref" };
|
||||
|
||||
static struct samsung_div_clock s3c2450_dividers[] __initdata = {
|
||||
DIV(0, "div_cam", "esysclk", CLKDIV1, 26, 4),
|
||||
DIV(0, "div_hsspi1_epll", "esysclk", CLKDIV2, 24, 2),
|
||||
DIV(0, "div_hsspi1_mpll", "msysclk", CLKDIV2, 16, 4),
|
||||
DIV(0, "div_i2s1", "esysclk", CLKDIV2, 12, 4),
|
||||
};
|
||||
|
||||
static struct samsung_mux_clock s3c2450_muxes[] __initdata = {
|
||||
MUX(0, "mux_cam", s3c2450_cam_p, CLKSRC, 20, 1),
|
||||
MUX(MUX_HSSPI1, "mux_hsspi1", s3c2450_hsspi1_p, CLKSRC, 19, 1),
|
||||
MUX(0, "mux_i2s1", i2s1_p, CLKSRC, 12, 2),
|
||||
};
|
||||
|
||||
static struct samsung_gate_clock s3c2450_gates[] __initdata = {
|
||||
GATE(SCLK_I2S1, "sclk_i2s1", "div_i2s1", SCLKCON, 5, 0, 0),
|
||||
GATE(HCLK_CFC, "cfc", "hclk", HCLKCON, 17, 0, 0),
|
||||
GATE(HCLK_CAM, "cam", "hclk", HCLKCON, 8, 0, 0),
|
||||
GATE(HCLK_DMA7, "dma7", "hclk", HCLKCON, 7, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(HCLK_DMA6, "dma6", "hclk", HCLKCON, 6, CLK_IGNORE_UNUSED, 0),
|
||||
GATE(PCLK_I2S1, "i2s1", "pclk", PCLKCON, 17, 0, 0),
|
||||
GATE(PCLK_I2C1, "i2c1", "pclk", PCLKCON, 16, 0, 0),
|
||||
GATE(PCLK_SPI1, "spi1", "pclk", PCLKCON, 14, 0, 0),
|
||||
};
|
||||
|
||||
static struct samsung_clock_alias s3c2450_aliases[] __initdata = {
|
||||
ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi"),
|
||||
ALIAS(PCLK_SPI1, "s3c2443-spi.1", "spi_busclk0"),
|
||||
ALIAS(MUX_HSSPI1, "s3c2443-spi.1", "spi_busclk2"),
|
||||
ALIAS(PCLK_I2C1, "s3c2410-i2c.1", "i2c"),
|
||||
};
|
||||
|
||||
static int s3c2443_restart(struct notifier_block *this,
|
||||
unsigned long mode, void *cmd)
|
||||
{
|
||||
__raw_writel(0x533c2443, reg_base + SWRST);
|
||||
return NOTIFY_DONE;
|
||||
}
|
||||
|
||||
static struct notifier_block s3c2443_restart_handler = {
|
||||
.notifier_call = s3c2443_restart,
|
||||
.priority = 129,
|
||||
};
|
||||
|
||||
/*
|
||||
* fixed rate clocks generated outside the soc
|
||||
* Only necessary until the devicetree-move is complete
|
||||
*/
|
||||
static struct samsung_fixed_rate_clock s3c2443_common_frate_clks[] __initdata = {
|
||||
FRATE(0, "xti", NULL, 0, 0),
|
||||
FRATE(0, "ext", NULL, 0, 0),
|
||||
FRATE(0, "ext_i2s", NULL, 0, 0),
|
||||
FRATE(0, "ext_uart", NULL, 0, 0),
|
||||
};
|
||||
|
||||
static void __init s3c2443_common_clk_register_fixed_ext(
|
||||
struct samsung_clk_provider *ctx, unsigned long xti_f)
|
||||
{
|
||||
s3c2443_common_frate_clks[0].fixed_rate = xti_f;
|
||||
samsung_clk_register_fixed_rate(ctx, s3c2443_common_frate_clks,
|
||||
ARRAY_SIZE(s3c2443_common_frate_clks));
|
||||
}
|
||||
|
||||
void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
|
||||
int current_soc,
|
||||
void __iomem *base)
|
||||
{
|
||||
struct samsung_clk_provider *ctx;
|
||||
int ret;
|
||||
reg_base = base;
|
||||
|
||||
if (np) {
|
||||
reg_base = of_iomap(np, 0);
|
||||
if (!reg_base)
|
||||
panic("%s: failed to map registers\n", __func__);
|
||||
}
|
||||
|
||||
ctx = samsung_clk_init(np, reg_base, NR_CLKS);
|
||||
|
||||
/* Register external clocks only in non-dt cases */
|
||||
if (!np)
|
||||
s3c2443_common_clk_register_fixed_ext(ctx, xti_f);
|
||||
|
||||
/* Register PLLs. */
|
||||
if (current_soc == S3C2416 || current_soc == S3C2450)
|
||||
samsung_clk_register_pll(ctx, s3c2416_pll_clks,
|
||||
ARRAY_SIZE(s3c2416_pll_clks), reg_base);
|
||||
else
|
||||
samsung_clk_register_pll(ctx, s3c2443_pll_clks,
|
||||
ARRAY_SIZE(s3c2443_pll_clks), reg_base);
|
||||
|
||||
/* Register common internal clocks. */
|
||||
samsung_clk_register_mux(ctx, s3c2443_common_muxes,
|
||||
ARRAY_SIZE(s3c2443_common_muxes));
|
||||
samsung_clk_register_div(ctx, s3c2443_common_dividers,
|
||||
ARRAY_SIZE(s3c2443_common_dividers));
|
||||
samsung_clk_register_gate(ctx, s3c2443_common_gates,
|
||||
ARRAY_SIZE(s3c2443_common_gates));
|
||||
samsung_clk_register_alias(ctx, s3c2443_common_aliases,
|
||||
ARRAY_SIZE(s3c2443_common_aliases));
|
||||
|
||||
/* Register SoC-specific clocks. */
|
||||
switch (current_soc) {
|
||||
case S3C2450:
|
||||
samsung_clk_register_div(ctx, s3c2450_dividers,
|
||||
ARRAY_SIZE(s3c2450_dividers));
|
||||
samsung_clk_register_mux(ctx, s3c2450_muxes,
|
||||
ARRAY_SIZE(s3c2450_muxes));
|
||||
samsung_clk_register_gate(ctx, s3c2450_gates,
|
||||
ARRAY_SIZE(s3c2450_gates));
|
||||
samsung_clk_register_alias(ctx, s3c2450_aliases,
|
||||
ARRAY_SIZE(s3c2450_aliases));
|
||||
fallthrough; /* as s3c2450 extends the s3c2416 clocks */
|
||||
case S3C2416:
|
||||
samsung_clk_register_div(ctx, s3c2416_dividers,
|
||||
ARRAY_SIZE(s3c2416_dividers));
|
||||
samsung_clk_register_mux(ctx, s3c2416_muxes,
|
||||
ARRAY_SIZE(s3c2416_muxes));
|
||||
samsung_clk_register_gate(ctx, s3c2416_gates,
|
||||
ARRAY_SIZE(s3c2416_gates));
|
||||
samsung_clk_register_alias(ctx, s3c2416_aliases,
|
||||
ARRAY_SIZE(s3c2416_aliases));
|
||||
break;
|
||||
case S3C2443:
|
||||
samsung_clk_register_div(ctx, s3c2443_dividers,
|
||||
ARRAY_SIZE(s3c2443_dividers));
|
||||
samsung_clk_register_gate(ctx, s3c2443_gates,
|
||||
ARRAY_SIZE(s3c2443_gates));
|
||||
samsung_clk_register_alias(ctx, s3c2443_aliases,
|
||||
ARRAY_SIZE(s3c2443_aliases));
|
||||
break;
|
||||
}
|
||||
|
||||
samsung_clk_sleep_init(reg_base, s3c2443_clk_regs,
|
||||
ARRAY_SIZE(s3c2443_clk_regs));
|
||||
|
||||
samsung_clk_of_add_provider(np, ctx);
|
||||
|
||||
ret = register_restart_handler(&s3c2443_restart_handler);
|
||||
if (ret)
|
||||
pr_warn("cannot register restart handler, %d\n", ret);
|
||||
}
|
||||
|
||||
static void __init s3c2416_clk_init(struct device_node *np)
|
||||
{
|
||||
s3c2443_common_clk_init(np, 0, S3C2416, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(s3c2416_clk, "samsung,s3c2416-clock", s3c2416_clk_init);
|
||||
|
||||
static void __init s3c2443_clk_init(struct device_node *np)
|
||||
{
|
||||
s3c2443_common_clk_init(np, 0, S3C2443, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(s3c2443_clk, "samsung,s3c2443-clock", s3c2443_clk_init);
|
||||
|
||||
static void __init s3c2450_clk_init(struct device_node *np)
|
||||
{
|
||||
s3c2443_common_clk_init(np, 0, S3C2450, NULL);
|
||||
}
|
||||
CLK_OF_DECLARE(s3c2450_clk, "samsung,s3c2450-clock", s3c2450_clk_init);
|
|
@ -1,19 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2020 Krzysztof Kozlowski <krzk@kernel.org>
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_PLATFORM_DATA_CLK_S3C2410_H_
|
||||
#define __LINUX_PLATFORM_DATA_CLK_S3C2410_H_
|
||||
|
||||
/**
|
||||
* struct s3c2410_clk_platform_data - platform data for S3C2410 clock driver
|
||||
*
|
||||
* @modify_misccr: Function to modify the MISCCR and return the new value
|
||||
*/
|
||||
struct s3c2410_clk_platform_data {
|
||||
unsigned int (*modify_misccr)(unsigned int clr, unsigned int chg);
|
||||
};
|
||||
|
||||
#endif /* __LINUX_PLATFORM_DATA_CLK_S3C2410_H_ */
|
||||
|
Loading…
Reference in a new issue