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[MIPS] Sibyte: Improve interrupt latency again for sb1250/bcm1480

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this patch restores the behaviour of the old (assembly-written)
interrupt handler, the handler is left as soon as a single interrupt
cause is handled.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thiemo Seufer 2006-07-05 14:26:38 +01:00 committed by Ralf Baechle
parent fc5d2d279f
commit 6e61e85b09
2 changed files with 9 additions and 8 deletions
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7
arch/mips/sibyte/bcm1480/irq.c
View file

@ -502,22 +502,23 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
#ifdef CONFIG_SIBYTE_BCM1480_PROF
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
sbprof_cpu_intr(exception_epc(regs));
else
#endif
if (pending & CAUSEF_IP4)
bcm1480_timer_interrupt(regs);
#ifdef CONFIG_SMP
if (pending & CAUSEF_IP3)
else if (pending & CAUSEF_IP3)
bcm1480_mailbox_interrupt(regs);
#endif
#ifdef CONFIG_KGDB
if (pending & CAUSEF_IP6)
else if (pending & CAUSEF_IP6)
bcm1480_kgdb_interrupt(regs); /* KGDB (uart 1) */
#endif
if (pending & CAUSEF_IP2) {
else if (pending & CAUSEF_IP2) {
unsigned long long mask_h, mask_l;
unsigned long base;

10
arch/mips/sibyte/sb1250/irq.c
View file

@ -460,25 +460,25 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
pending = read_c0_cause();
#ifdef CONFIG_SIBYTE_SB1250_PROF
if (pending & CAUSEF_IP7) { /* Cpu performance counter interrupt */
if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
sbprof_cpu_intr(exception_epc(regs));
}
else
#endif
if (pending & CAUSEF_IP4)
sb1250_timer_interrupt(regs);
#ifdef CONFIG_SMP
if (pending & CAUSEF_IP3)
else if (pending & CAUSEF_IP3)
sb1250_mailbox_interrupt(regs);
#endif
#ifdef CONFIG_KGDB
if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
else if (pending & CAUSEF_IP6) /* KGDB (uart 1) */
sb1250_kgdb_interrupt(regs);
#endif
if (pending & CAUSEF_IP2) {
else if (pending & CAUSEF_IP2) {
unsigned long long mask;
/*