i2c: keba: Add KEBA I2C controller support
The KEBA I2C controller is found in the system FPGA of KEBA PLC devices. It is used to connect EEPROMs and hardware monitoring chips. The It is a simple I2C controller with a fixed bus speed of 100 kbit/s. The whole message transmission is executed by the driver. The driver triggers all steps over control, status and data register. There are no FIFOs or interrupts. Signed-off-by: Gerhard Engleder <eg@keba.com> Signed-off-by: Andi Shyti <andi.shyti@kernel.org>
This commit is contained in:
Gerhard Engleder
Andi Shyti
parent
43457ada98
commit
c7e08c816c
3 changed files with 610 additions and 0 deletions
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@ -779,6 +779,17 @@ config I2C_JZ4780
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If you don't know what to do here, say N.
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config I2C_KEBA
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tristate "KEBA I2C controller support"
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depends on HAS_IOMEM
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select AUXILIARY_BUS
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help
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This driver supports the I2C controller found in KEBA system FPGA
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devices.
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This driver can also be built as a module. If so, the module
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will be called i2c-keba.
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config I2C_KEMPLD
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tristate "Kontron COM I2C Controller"
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depends on MFD_KEMPLD
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@ -76,6 +76,7 @@ obj-$(CONFIG_I2C_IMX) += i2c-imx.o
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obj-$(CONFIG_I2C_IMX_LPI2C) += i2c-imx-lpi2c.o
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obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
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obj-$(CONFIG_I2C_JZ4780) += i2c-jz4780.o
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obj-$(CONFIG_I2C_KEBA) += i2c-keba.o
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obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
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obj-$(CONFIG_I2C_LPC2K) += i2c-lpc2k.o
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obj-$(CONFIG_I2C_LS2X) += i2c-ls2x.o
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598
drivers/i2c/busses/i2c-keba.c
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598
drivers/i2c/busses/i2c-keba.c
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@ -0,0 +1,598 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) KEBA Industrial Automation Gmbh 2024
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*
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* Driver for KEBA I2C controller FPGA IP core
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*/
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#include <linux/i2c.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/misc/keba.h>
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#define KI2C "i2c-keba"
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#define KI2C_CAPABILITY_REG 0x02
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#define KI2C_CAPABILITY_CRYPTO 0x01
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#define KI2C_CAPABILITY_DC 0x02
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#define KI2C_CONTROL_REG 0x04
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#define KI2C_CONTROL_MEN 0x01
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#define KI2C_CONTROL_MSTA 0x02
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#define KI2C_CONTROL_RSTA 0x04
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#define KI2C_CONTROL_MTX 0x08
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#define KI2C_CONTROL_TXAK 0x10
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#define KI2C_CONTROL_DISABLE 0x00
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#define KI2C_CONTROL_DC_REG 0x05
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#define KI2C_CONTROL_DC_SDA 0x01
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#define KI2C_CONTROL_DC_SCL 0x02
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#define KI2C_STATUS_REG 0x08
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#define KI2C_STATUS_IN_USE 0x01
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#define KI2C_STATUS_ACK_CYC 0x02
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#define KI2C_STATUS_RXAK 0x04
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#define KI2C_STATUS_MCF 0x08
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#define KI2C_STATUS_DC_REG 0x09
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#define KI2C_STATUS_DC_SDA 0x01
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#define KI2C_STATUS_DC_SCL 0x02
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#define KI2C_DATA_REG 0x0c
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#define KI2C_INUSE_SLEEP_US (2 * USEC_PER_MSEC)
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#define KI2C_INUSE_TIMEOUT_US (10 * USEC_PER_SEC)
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#define KI2C_POLL_DELAY_US 5
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struct ki2c {
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struct keba_i2c_auxdev *auxdev;
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void __iomem *base;
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struct i2c_adapter adapter;
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struct i2c_client **client;
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int client_size;
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};
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static int ki2c_inuse_lock(struct ki2c *ki2c)
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{
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u8 sts;
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int ret;
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/*
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* The I2C controller has an IN_USE bit for locking access to the
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* controller. This enables the use of I2C controller by other none
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* Linux processors.
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*
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* If the I2C controller is free, then the first read returns
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* IN_USE == 0. After that the I2C controller is locked and further
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* reads of IN_USE return 1.
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*
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* The I2C controller is unlocked by writing 1 into IN_USE.
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*
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* The IN_USE bit acts as a hardware semaphore for the I2C controller.
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* Poll for semaphore, but sleep while polling to free the CPU.
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*/
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ret = readb_poll_timeout(ki2c->base + KI2C_STATUS_REG,
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sts, (sts & KI2C_STATUS_IN_USE) == 0,
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KI2C_INUSE_SLEEP_US, KI2C_INUSE_TIMEOUT_US);
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if (ret)
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dev_err(&ki2c->auxdev->auxdev.dev, "%s err!\n", __func__);
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return ret;
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}
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static void ki2c_inuse_unlock(struct ki2c *ki2c)
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{
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/* unlock the controller by writing 1 into IN_USE */
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iowrite8(KI2C_STATUS_IN_USE, ki2c->base + KI2C_STATUS_REG);
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}
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static int ki2c_wait_for_bit(void __iomem *addr, u8 mask, unsigned long timeout)
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{
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u8 val;
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return readb_poll_timeout(addr, val, (val & mask), KI2C_POLL_DELAY_US,
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jiffies_to_usecs(timeout));
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}
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static int ki2c_wait_for_mcf(struct ki2c *ki2c)
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{
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return ki2c_wait_for_bit(ki2c->base + KI2C_STATUS_REG, KI2C_STATUS_MCF,
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ki2c->adapter.timeout);
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}
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static int ki2c_wait_for_data(struct ki2c *ki2c)
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{
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int ret;
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ret = ki2c_wait_for_mcf(ki2c);
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if (ret < 0)
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return ret;
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return ki2c_wait_for_bit(ki2c->base + KI2C_STATUS_REG,
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KI2C_STATUS_ACK_CYC,
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ki2c->adapter.timeout);
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}
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static int ki2c_wait_for_data_ack(struct ki2c *ki2c)
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{
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unsigned int reg;
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int ret;
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ret = ki2c_wait_for_data(ki2c);
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if (ret < 0)
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return ret;
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/* RXAK == 0 means ACK reveived */
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reg = ioread8(ki2c->base + KI2C_STATUS_REG);
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if (reg & KI2C_STATUS_RXAK)
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return -EIO;
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return 0;
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}
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static int ki2c_has_capability(struct ki2c *ki2c, unsigned int cap)
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{
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unsigned int reg = ioread8(ki2c->base + KI2C_CAPABILITY_REG);
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return (reg & cap) != 0;
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}
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static int ki2c_get_scl(struct ki2c *ki2c)
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{
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unsigned int reg = ioread8(ki2c->base + KI2C_STATUS_DC_REG);
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/* capability KI2C_CAPABILITY_DC required */
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return (reg & KI2C_STATUS_DC_SCL) != 0;
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}
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static int ki2c_get_sda(struct ki2c *ki2c)
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{
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unsigned int reg = ioread8(ki2c->base + KI2C_STATUS_DC_REG);
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/* capability KI2C_CAPABILITY_DC required */
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return (reg & KI2C_STATUS_DC_SDA) != 0;
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}
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static void ki2c_set_scl(struct ki2c *ki2c, int val)
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{
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u8 control_dc;
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/* capability KI2C_CAPABILITY_DC and KI2C_CONTROL_MEN = 0 reqired */
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control_dc = ioread8(ki2c->base + KI2C_CONTROL_DC_REG);
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if (val)
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control_dc |= KI2C_CONTROL_DC_SCL;
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else
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control_dc &= ~KI2C_CONTROL_DC_SCL;
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iowrite8(control_dc, ki2c->base + KI2C_CONTROL_DC_REG);
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}
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/*
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* Resetting bus bitwise is done by checking SDA and applying clock cycles as
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* long as SDA is low. 9 clock cycles are applied at most.
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*
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* Clock cycles are generated and udelay() determines the duration of clock
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* cycles. Generated clock rate is 100 KHz and so duration of both clock levels
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* is: delay in ns = (10^6 / 100) / 2
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*/
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#define KI2C_RECOVERY_CLK_CNT (9 * 2)
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#define KI2C_RECOVERY_UDELAY 5
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static int ki2c_reset_bus_bitwise(struct ki2c *ki2c)
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{
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int val = 1;
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int ret = 0;
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int i;
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/* disable I2C controller (MEN = 0) to get direct access to SCL/SDA */
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iowrite8(0, ki2c->base + KI2C_CONTROL_REG);
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/* generate clock cycles */
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ki2c_set_scl(ki2c, val);
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udelay(KI2C_RECOVERY_UDELAY);
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for (i = 0; i < KI2C_RECOVERY_CLK_CNT; i++) {
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if (val) {
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/* SCL shouldn't be low here */
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if (!ki2c_get_scl(ki2c)) {
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dev_err(&ki2c->auxdev->auxdev.dev,
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"SCL is stuck low!\n");
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ret = -EBUSY;
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break;
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}
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/* break if SDA is high */
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if (ki2c_get_sda(ki2c))
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break;
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}
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val = !val;
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ki2c_set_scl(ki2c, val);
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udelay(KI2C_RECOVERY_UDELAY);
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}
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if (!ki2c_get_sda(ki2c)) {
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dev_err(&ki2c->auxdev->auxdev.dev, "SDA is still low!\n");
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ret = -EBUSY;
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}
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/* reenable controller */
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iowrite8(KI2C_CONTROL_MEN, ki2c->base + KI2C_CONTROL_REG);
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return ret;
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}
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/*
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* Resetting bus bytewise is done by writing start bit, 9 data bits and stop
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* bit.
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*
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* This is not 100% safe. If target is an EEPROM and a write access was
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* interrupted during the ACK cycle, this approach might not be able to recover
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* the bus. The reason is, that after the 9 clock cycles the EEPROM will be in
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* ACK cycle again and will hold SDA low like it did before the start of the
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* routine. Furthermore the EEPROM might get written one additional byte with
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* 0xff into it. Thus, use bitwise approach whenever possible, especially when
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* EEPROMs are on the bus.
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*/
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static int ki2c_reset_bus_bytewise(struct ki2c *ki2c)
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{
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int ret;
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/* hold data line high for 9 clock cycles */
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iowrite8(0xFF, ki2c->base + KI2C_DATA_REG);
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/* create start condition */
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iowrite8(KI2C_CONTROL_MEN | KI2C_CONTROL_MTX | KI2C_CONTROL_MSTA | KI2C_CONTROL_TXAK,
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ki2c->base + KI2C_CONTROL_REG);
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ret = ki2c_wait_for_mcf(ki2c);
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if (ret < 0) {
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dev_err(&ki2c->auxdev->auxdev.dev, "Start condition failed\n");
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return ret;
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}
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/* create stop condition */
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iowrite8(KI2C_CONTROL_MEN | KI2C_CONTROL_MTX | KI2C_CONTROL_TXAK,
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ki2c->base + KI2C_CONTROL_REG);
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ret = ki2c_wait_for_mcf(ki2c);
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if (ret < 0)
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dev_err(&ki2c->auxdev->auxdev.dev, "Stop condition failed\n");
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return ret;
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}
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static int ki2c_reset_bus(struct ki2c *ki2c)
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{
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int ret;
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ret = ki2c_inuse_lock(ki2c);
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if (ret < 0)
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return ret;
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/*
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* If the I2C controller is capable of direct control of SCL/SDA, then a
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* bitwise reset is used. Otherwise fall back to bytewise reset.
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*/
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if (ki2c_has_capability(ki2c, KI2C_CAPABILITY_DC))
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ret = ki2c_reset_bus_bitwise(ki2c);
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else
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ret = ki2c_reset_bus_bytewise(ki2c);
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ki2c_inuse_unlock(ki2c);
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return ret;
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}
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static void ki2c_write_target_addr(struct ki2c *ki2c, struct i2c_msg *m)
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{
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u8 addr;
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addr = m->addr << 1;
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/* Bit 0 signals RD/WR */
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if (m->flags & I2C_M_RD)
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addr |= 0x01;
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iowrite8(addr, ki2c->base + KI2C_DATA_REG);
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}
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static int ki2c_start_addr(struct ki2c *ki2c, struct i2c_msg *m)
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{
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int ret;
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/*
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* Store target address byte in the controller. This has to be done
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* before sending START condition.
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*/
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ki2c_write_target_addr(ki2c, m);
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/* enable controller for TX */
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iowrite8(KI2C_CONTROL_MEN | KI2C_CONTROL_MTX,
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ki2c->base + KI2C_CONTROL_REG);
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/* send START condition and target address byte */
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iowrite8(KI2C_CONTROL_MEN | KI2C_CONTROL_MTX | KI2C_CONTROL_MSTA,
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ki2c->base + KI2C_CONTROL_REG);
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ret = ki2c_wait_for_data_ack(ki2c);
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if (ret < 0)
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/*
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* For EEPROMs this is normal behavior during internal write
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* operation.
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*/
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dev_dbg(&ki2c->auxdev->auxdev.dev,
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"%s wait for ACK err at 0x%02x!\n", __func__, m->addr);
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return ret;
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}
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static int ki2c_repstart_addr(struct ki2c *ki2c, struct i2c_msg *m)
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{
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int ret;
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/* repeated start and write is not supported */
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if ((m->flags & I2C_M_RD) == 0) {
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dev_err(&ki2c->auxdev->auxdev.dev,
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"Repeated start not supported for writes\n");
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return -EINVAL;
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}
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/* send repeated start */
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iowrite8(KI2C_CONTROL_MEN | KI2C_CONTROL_MSTA | KI2C_CONTROL_RSTA,
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ki2c->base + KI2C_CONTROL_REG);
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ret = ki2c_wait_for_mcf(ki2c);
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if (ret < 0) {
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dev_err(&ki2c->auxdev->auxdev.dev,
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"%s wait for MCF err at 0x%02x!\n", __func__, m->addr);
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return ret;
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}
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/* write target-address byte */
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ki2c_write_target_addr(ki2c, m);
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ret = ki2c_wait_for_data_ack(ki2c);
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if (ret < 0)
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dev_err(&ki2c->auxdev->auxdev.dev,
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"%s wait for ACK err at 0x%02x!\n", __func__, m->addr);
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return ret;
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}
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static void ki2c_stop(struct ki2c *ki2c)
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{
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iowrite8(KI2C_CONTROL_MEN, ki2c->base + KI2C_CONTROL_REG);
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ki2c_wait_for_mcf(ki2c);
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}
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static int ki2c_write(struct ki2c *ki2c, const u8 *data, int len)
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{
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int ret;
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int i;
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for (i = 0; i < len; i++) {
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/* write data byte */
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iowrite8(data[i], ki2c->base + KI2C_DATA_REG);
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ret = ki2c_wait_for_data_ack(ki2c);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int ki2c_read(struct ki2c *ki2c, u8 *data, int len)
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{
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u8 control;
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int ret;
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int i;
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if (len == 0)
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return 0; /* nothing to do */
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control = KI2C_CONTROL_MEN | KI2C_CONTROL_MSTA;
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/* if just one byte => send tx-nack after transfer */
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if (len == 1)
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control |= KI2C_CONTROL_TXAK;
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iowrite8(control, ki2c->base + KI2C_CONTROL_REG);
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/* dummy read to start transfer on bus */
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ioread8(ki2c->base + KI2C_DATA_REG);
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for (i = 0; i < len; i++) {
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ret = ki2c_wait_for_data(ki2c);
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if (ret < 0)
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return ret;
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if (i == len - 2)
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/* send tx-nack after transfer of last byte */
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iowrite8(KI2C_CONTROL_MEN | KI2C_CONTROL_MSTA | KI2C_CONTROL_TXAK,
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ki2c->base + KI2C_CONTROL_REG);
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else if (i == len - 1)
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/*
|
||||
* switch to TX on last byte, so that reading DATA
|
||||
* register does not trigger another read transfer
|
||||
*/
|
||||
iowrite8(KI2C_CONTROL_MEN | KI2C_CONTROL_MSTA | KI2C_CONTROL_MTX,
|
||||
ki2c->base + KI2C_CONTROL_REG);
|
||||
|
||||
/* read byte and start next transfer (if not last byte) */
|
||||
data[i] = ioread8(ki2c->base + KI2C_DATA_REG);
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
static int ki2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
|
||||
{
|
||||
struct ki2c *ki2c = i2c_get_adapdata(adap);
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
ret = ki2c_inuse_lock(ki2c);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < num; i++) {
|
||||
struct i2c_msg *m = &msgs[i];
|
||||
|
||||
if (i == 0)
|
||||
ret = ki2c_start_addr(ki2c, m);
|
||||
else
|
||||
ret = ki2c_repstart_addr(ki2c, m);
|
||||
if (ret < 0)
|
||||
break;
|
||||
|
||||
if (m->flags & I2C_M_RD)
|
||||
ret = ki2c_read(ki2c, m->buf, m->len);
|
||||
else
|
||||
ret = ki2c_write(ki2c, m->buf, m->len);
|
||||
if (ret < 0)
|
||||
break;
|
||||
}
|
||||
|
||||
ki2c_stop(ki2c);
|
||||
|
||||
ki2c_inuse_unlock(ki2c);
|
||||
|
||||
return ret < 0 ? ret : num;
|
||||
}
|
||||
|
||||
static void ki2c_unregister_devices(struct ki2c *ki2c)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ki2c->client_size; i++) {
|
||||
struct i2c_client *client = ki2c->client[i];
|
||||
|
||||
if (client)
|
||||
i2c_unregister_device(client);
|
||||
}
|
||||
}
|
||||
|
||||
static int ki2c_register_devices(struct ki2c *ki2c)
|
||||
{
|
||||
struct i2c_board_info *info = ki2c->auxdev->info;
|
||||
int i;
|
||||
|
||||
/* register all known I2C devices */
|
||||
for (i = 0; i < ki2c->client_size; i++) {
|
||||
struct i2c_client *client;
|
||||
unsigned short const addr_list[2] = { info[i].addr,
|
||||
I2C_CLIENT_END };
|
||||
|
||||
client = i2c_new_scanned_device(&ki2c->adapter, &info[i],
|
||||
addr_list, NULL);
|
||||
if (!IS_ERR(client)) {
|
||||
ki2c->client[i] = client;
|
||||
} else if (PTR_ERR(client) != -ENODEV) {
|
||||
ki2c->client_size = i;
|
||||
ki2c_unregister_devices(ki2c);
|
||||
|
||||
return PTR_ERR(client);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u32 ki2c_func(struct i2c_adapter *adap)
|
||||
{
|
||||
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm ki2c_algo = {
|
||||
.master_xfer = ki2c_xfer,
|
||||
.functionality = ki2c_func,
|
||||
};
|
||||
|
||||
static int ki2c_probe(struct auxiliary_device *auxdev,
|
||||
const struct auxiliary_device_id *id)
|
||||
{
|
||||
struct device *dev = &auxdev->dev;
|
||||
struct i2c_adapter *adap;
|
||||
struct ki2c *ki2c;
|
||||
int ret;
|
||||
|
||||
ki2c = devm_kzalloc(dev, sizeof(*ki2c), GFP_KERNEL);
|
||||
if (!ki2c)
|
||||
return -ENOMEM;
|
||||
ki2c->auxdev = container_of(auxdev, struct keba_i2c_auxdev, auxdev);
|
||||
ki2c->client = devm_kcalloc(dev, ki2c->auxdev->info_size,
|
||||
sizeof(*ki2c->client), GFP_KERNEL);
|
||||
if (!ki2c->client)
|
||||
return -ENOMEM;
|
||||
ki2c->client_size = ki2c->auxdev->info_size;
|
||||
auxiliary_set_drvdata(auxdev, ki2c);
|
||||
|
||||
ki2c->base = devm_ioremap_resource(dev, &ki2c->auxdev->io);
|
||||
if (IS_ERR(ki2c->base))
|
||||
return PTR_ERR(ki2c->base);
|
||||
|
||||
adap = &ki2c->adapter;
|
||||
strscpy(adap->name, "KEBA I2C adapter", sizeof(adap->name));
|
||||
adap->owner = THIS_MODULE;
|
||||
adap->class = I2C_CLASS_HWMON;
|
||||
adap->algo = &ki2c_algo;
|
||||
adap->dev.parent = dev;
|
||||
|
||||
i2c_set_adapdata(adap, ki2c);
|
||||
|
||||
/* enable controller */
|
||||
iowrite8(KI2C_CONTROL_MEN, ki2c->base + KI2C_CONTROL_REG);
|
||||
|
||||
/* reset bus before probing I2C devices */
|
||||
ret = ki2c_reset_bus(ki2c);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
ret = devm_i2c_add_adapter(dev, adap);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to add adapter (%d)!\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
ret = ki2c_register_devices(ki2c);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register devices (%d)!\n", ret);
|
||||
goto out;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out:
|
||||
iowrite8(KI2C_CONTROL_DISABLE, ki2c->base + KI2C_CONTROL_REG);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void ki2c_remove(struct auxiliary_device *auxdev)
|
||||
{
|
||||
struct ki2c *ki2c = auxiliary_get_drvdata(auxdev);
|
||||
|
||||
ki2c_unregister_devices(ki2c);
|
||||
|
||||
/* disable controller */
|
||||
iowrite8(KI2C_CONTROL_DISABLE, ki2c->base + KI2C_CONTROL_REG);
|
||||
|
||||
auxiliary_set_drvdata(auxdev, NULL);
|
||||
}
|
||||
|
||||
static const struct auxiliary_device_id ki2c_devtype_aux[] = {
|
||||
{ .name = "keba.i2c" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(auxiliary, ki2c_devtype_aux);
|
||||
|
||||
static struct auxiliary_driver ki2c_driver_aux = {
|
||||
.name = KI2C,
|
||||
.id_table = ki2c_devtype_aux,
|
||||
.probe = ki2c_probe,
|
||||
.remove = ki2c_remove,
|
||||
};
|
||||
module_auxiliary_driver(ki2c_driver_aux);
|
||||
|
||||
MODULE_AUTHOR("Gerhard Engleder <eg@keba.com>");
|
||||
MODULE_DESCRIPTION("KEBA I2C bus controller driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in a new issue