arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register
Enable all remaining feature bits like EVT, CCIDX, LSM, HPDS, CnP, XNX, SpecSEI in ID_MMFR4 register per ARM DDI 0487F.a. Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Link: https://lore.kernel.org/r/1589881254-10082-9-git-send-email-anshuman.khandual@arm.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -794,6 +794,14 @@
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#define ID_ISAR6_DP_SHIFT 4
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#define ID_ISAR6_JSCVT_SHIFT 0
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#define ID_MMFR4_EVT_SHIFT 28
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#define ID_MMFR4_CCIDX_SHIFT 24
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#define ID_MMFR4_LSM_SHIFT 20
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#define ID_MMFR4_HPDS_SHIFT 16
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#define ID_MMFR4_CNP_SHIFT 12
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#define ID_MMFR4_XNX_SHIFT 8
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#define ID_MMFR4_SPECSEI_SHIFT 0
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#define ID_MMFR5_ETS_SHIFT 0
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#define ID_PFR0_DIT_SHIFT 24
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@ -392,7 +392,20 @@ static const struct arm64_ftr_bits ftr_id_isar5[] = {
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};
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static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EVT_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CCIDX_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_LSM_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_HPDS_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_CNP_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_XNX_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), /* ac2 */
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/*
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* SpecSEI = 1 indicates that the PE might generate an SError on an
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* external abort on speculative read. It is safe to assume that an
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* SError might be generated than it will not be. Hence it has been
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* classified as FTR_HIGHER_SAFE.
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*/
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_SPECSEI_SHIFT, 4, 0),
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ARM64_FTR_END,
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};
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