ced3068344
Currently the divider selection logic blindly divides the parent_rate by the clk rate and gives the divider value for the divider clocks which do not have the CLK_SET_RATE_PARENT flag set. Add the clk divider table parsing to get the closest divider available in the table provided via Device tree. The code is pretty much taken from: drivers/clk/clk-divider.c. and used here to fix up the best divider selection logic. Signed-off-by: Keerthy <j-keerthy@ti.com> Reported-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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| .. | ||
| adpll.c | ||
| apll.c | ||
| autoidle.c | ||
| clk-2xxx.c | ||
| clk-3xxx-legacy.c | ||
| clk-3xxx.c | ||
| clk-7xx.c | ||
| clk-33xx.c | ||
| clk-43xx.c | ||
| clk-44xx.c | ||
| clk-54xx.c | ||
| clk-814x.c | ||
| clk-816x.c | ||
| clk-dra7-atl.c | ||
| clk.c | ||
| clkt_dflt.c | ||
| clkt_dpll.c | ||
| clkt_iclk.c | ||
| clock.h | ||
| clockdomain.c | ||
| composite.c | ||
| divider.c | ||
| dpll.c | ||
| dpll3xxx.c | ||
| dpll44xx.c | ||
| fapll.c | ||
| fixed-factor.c | ||
| gate.c | ||
| interface.c | ||
| Kconfig | ||
| Makefile | ||
| mux.c | ||