1ba6ab11d8
We currently keep 2 lists of PCI devices in the system, one in the driver core, and one all on its own. This second list is sorted at boot time, in "BIOS" order, to try to remain compatible with older kernels (2.2 and earlier days). There was also a "nosort" option to turn this sorting off, to remain compatible with even older kernel versions, but that just ends up being what we have been doing from 2.5 days... Unfortunately, the second list of devices is not really ever used to determine the probing order of PCI devices or drivers[1]. That is done using the driver core list instead. This change happened back in the early 2.5 days. Relying on BIOS ording for the binding of drivers to specific device names is problematic for many reasons, and userspace tools like udev exist to properly name devices in a persistant manner if that is needed, no reliance on the BIOS is needed. Matt Domsch and others at Dell noticed this back in 2006, and added a boot option to sort the PCI device lists (both of them) in a breadth-first manner to help remain compatible with the 2.4 order, if needed for any reason. This option is not going away, as some systems rely on them. This patch removes the sorting of the internal PCI device list in "BIOS" mode, as it's not needed at all anymore, and hasn't for many years. I've also removed the PCI flags for this from some other arches that for some reason defined them, but never used them. This should not change the ordering of any drivers or device probing. [1] The old-style pci_get_device and pci_find_device() still used this sorting order, but there are very few drivers that use these functions, as they are deprecated for use in this manner. If for some reason, a driver rely on the order and uses these functions, the breadth-first boot option will resolve any problem. Cc: Matt Domsch <Matt_Domsch@dell.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
148 lines
3.7 KiB
C
148 lines
3.7 KiB
C
/*
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* Low-Level PCI Access for i386 machines.
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*
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* (c) 1999 Martin Mares <mj@ucw.cz>
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*/
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...)
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#endif
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#define PCI_PROBE_BIOS 0x0001
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#define PCI_PROBE_CONF1 0x0002
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#define PCI_PROBE_CONF2 0x0004
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#define PCI_PROBE_MMCONF 0x0008
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#define PCI_PROBE_MASK 0x000f
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#define PCI_PROBE_NOEARLY 0x0010
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#define PCI_NO_CHECKS 0x0400
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#define PCI_USE_PIRQ_MASK 0x0800
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#define PCI_ASSIGN_ROMS 0x1000
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#define PCI_BIOS_IRQ_SCAN 0x2000
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#define PCI_ASSIGN_ALL_BUSSES 0x4000
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#define PCI_CAN_SKIP_ISA_ALIGN 0x8000
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#define PCI_USE__CRS 0x10000
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extern unsigned int pci_probe;
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extern unsigned long pirq_table_addr;
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enum pci_bf_sort_state {
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pci_bf_sort_default,
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pci_force_nobf,
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pci_force_bf,
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pci_dmi_bf,
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};
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/* pci-i386.c */
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extern unsigned int pcibios_max_latency;
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void pcibios_resource_survey(void);
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int pcibios_enable_resources(struct pci_dev *, int);
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/* pci-pc.c */
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extern int pcibios_last_bus;
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extern struct pci_bus *pci_root_bus;
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extern struct pci_ops pci_root_ops;
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/* pci-irq.c */
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struct irq_info {
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u8 bus, devfn; /* Bus, device and function */
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struct {
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u8 link; /* IRQ line ID, chipset dependent, 0=not routed */
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u16 bitmap; /* Available IRQs */
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} __attribute__((packed)) irq[4];
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u8 slot; /* Slot number, 0=onboard */
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u8 rfu;
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} __attribute__((packed));
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struct irq_routing_table {
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u32 signature; /* PIRQ_SIGNATURE should be here */
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u16 version; /* PIRQ_VERSION */
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u16 size; /* Table size in bytes */
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u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
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u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
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u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */
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u32 miniport_data; /* Crap */
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u8 rfu[11];
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u8 checksum; /* Modulo 256 checksum must give zero */
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struct irq_info slots[0];
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} __attribute__((packed));
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extern unsigned int pcibios_irq_mask;
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extern int pcibios_scanned;
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extern spinlock_t pci_config_lock;
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extern int (*pcibios_enable_irq)(struct pci_dev *dev);
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extern void (*pcibios_disable_irq)(struct pci_dev *dev);
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struct pci_raw_ops {
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int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 *val);
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int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
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int reg, int len, u32 val);
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};
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extern struct pci_raw_ops *raw_pci_ops;
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extern struct pci_raw_ops *raw_pci_ext_ops;
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extern struct pci_raw_ops pci_direct_conf1;
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extern int pci_direct_probe(void);
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extern void pci_direct_init(int type);
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extern void pci_pcbios_init(void);
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extern void pci_mmcfg_init(int type);
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/* pci-mmconfig.c */
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extern int __init pci_mmcfg_arch_init(void);
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/*
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* AMD Fam10h CPUs are buggy, and cannot access MMIO config space
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* on their northbrige except through the * %eax register. As such, you MUST
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* NOT use normal IOMEM accesses, you need to only use the magic mmio-config
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* accessor functions.
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* In fact just use pci_config_*, nothing else please.
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*/
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static inline unsigned char mmio_config_readb(void __iomem *pos)
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{
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u8 val;
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asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned short mmio_config_readw(void __iomem *pos)
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{
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u16 val;
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asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline unsigned int mmio_config_readl(void __iomem *pos)
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{
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u32 val;
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asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
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return val;
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}
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static inline void mmio_config_writeb(void __iomem *pos, u8 val)
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{
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asm volatile("movb %%al,(%1)" :: "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writew(void __iomem *pos, u16 val)
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{
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asm volatile("movw %%ax,(%1)" :: "a" (val), "r" (pos) : "memory");
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}
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static inline void mmio_config_writel(void __iomem *pos, u32 val)
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{
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asm volatile("movl %%eax,(%1)" :: "a" (val), "r" (pos) : "memory");
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}
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