a19bffb10c
When host system is under heavy load and the NPU is already running on the lowest frequency, PUNIT may request Duty Cycle Throttling (DCT). This will further reduce NPU power usage. PUNIT requests DCT mode using Survabilty IRQ and mailbox register. The driver then issues a JSM message to the FW that enables the DCT mode. If the NPU resets while in DCT mode, the driver request DCT mode during FW boot. Also add debugfs "dct" file that allows to set arbitrary DCT percentage, which is used by driver tests. Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> Reviewed-by: Wachowski, Karol <karol.wachowski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240611120433.1012423-7-jacek.lawrynowicz@linux.intel.com
160 lines
3.8 KiB
C
160 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2020-2024 Intel Corporation
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*/
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#ifndef __IVPU_HW_H__
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#define __IVPU_HW_H__
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#include <linux/kfifo.h>
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#include "ivpu_drv.h"
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#include "ivpu_hw_btrs.h"
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#include "ivpu_hw_ip.h"
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#define IVPU_HW_IRQ_FIFO_LENGTH 1024
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#define IVPU_HW_IRQ_SRC_IPC 1
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#define IVPU_HW_IRQ_SRC_MMU_EVTQ 2
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#define IVPU_HW_IRQ_SRC_DCT 3
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struct ivpu_addr_range {
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resource_size_t start;
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resource_size_t end;
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};
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struct ivpu_hw_info {
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struct {
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bool (*btrs_irq_handler)(struct ivpu_device *vdev, int irq);
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bool (*ip_irq_handler)(struct ivpu_device *vdev, int irq);
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DECLARE_KFIFO(fifo, u8, IVPU_HW_IRQ_FIFO_LENGTH);
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} irq;
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struct {
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struct ivpu_addr_range global;
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struct ivpu_addr_range user;
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struct ivpu_addr_range shave;
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struct ivpu_addr_range dma;
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} ranges;
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struct {
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u8 min_ratio;
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u8 max_ratio;
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/*
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* Pll ratio for the efficiency frequency. The VPU has optimum
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* performance to power ratio at this frequency.
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*/
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u8 pn_ratio;
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u32 profiling_freq;
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} pll;
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u32 tile_fuse;
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u32 sched_mode;
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u32 sku;
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u16 config;
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int dma_bits;
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ktime_t d0i3_entry_host_ts;
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u64 d0i3_entry_vpu_ts;
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};
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int ivpu_hw_init(struct ivpu_device *vdev);
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int ivpu_hw_power_up(struct ivpu_device *vdev);
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int ivpu_hw_power_down(struct ivpu_device *vdev);
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int ivpu_hw_reset(struct ivpu_device *vdev);
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int ivpu_hw_boot_fw(struct ivpu_device *vdev);
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void ivpu_hw_profiling_freq_drive(struct ivpu_device *vdev, bool enable);
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void ivpu_irq_handlers_init(struct ivpu_device *vdev);
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void ivpu_hw_irq_enable(struct ivpu_device *vdev);
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void ivpu_hw_irq_disable(struct ivpu_device *vdev);
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irqreturn_t ivpu_hw_irq_handler(int irq, void *ptr);
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static inline u32 ivpu_hw_btrs_irq_handler(struct ivpu_device *vdev, int irq)
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{
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return vdev->hw->irq.btrs_irq_handler(vdev, irq);
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}
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static inline u32 ivpu_hw_ip_irq_handler(struct ivpu_device *vdev, int irq)
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{
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return vdev->hw->irq.ip_irq_handler(vdev, irq);
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}
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static inline void ivpu_hw_range_init(struct ivpu_addr_range *range, u64 start, u64 size)
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{
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range->start = start;
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range->end = start + size;
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}
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static inline u64 ivpu_hw_range_size(const struct ivpu_addr_range *range)
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{
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return range->end - range->start;
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}
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static inline u32 ivpu_hw_ratio_to_freq(struct ivpu_device *vdev, u32 ratio)
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{
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return ivpu_hw_btrs_ratio_to_freq(vdev, ratio);
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}
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static inline void ivpu_hw_irq_clear(struct ivpu_device *vdev)
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{
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ivpu_hw_ip_irq_clear(vdev);
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}
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static inline u32 ivpu_hw_pll_freq_get(struct ivpu_device *vdev)
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{
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return ivpu_hw_btrs_pll_freq_get(vdev);
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}
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static inline u32 ivpu_hw_profiling_freq_get(struct ivpu_device *vdev)
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{
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return vdev->hw->pll.profiling_freq;
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}
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static inline void ivpu_hw_diagnose_failure(struct ivpu_device *vdev)
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{
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ivpu_hw_ip_diagnose_failure(vdev);
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ivpu_hw_btrs_diagnose_failure(vdev);
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}
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static inline u32 ivpu_hw_telemetry_offset_get(struct ivpu_device *vdev)
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{
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return ivpu_hw_btrs_telemetry_offset_get(vdev);
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}
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static inline u32 ivpu_hw_telemetry_size_get(struct ivpu_device *vdev)
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{
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return ivpu_hw_btrs_telemetry_size_get(vdev);
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}
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static inline u32 ivpu_hw_telemetry_enable_get(struct ivpu_device *vdev)
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{
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return ivpu_hw_btrs_telemetry_enable_get(vdev);
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}
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static inline bool ivpu_hw_is_idle(struct ivpu_device *vdev)
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{
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return ivpu_hw_btrs_is_idle(vdev);
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}
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static inline int ivpu_hw_wait_for_idle(struct ivpu_device *vdev)
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{
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return ivpu_hw_btrs_wait_for_idle(vdev);
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}
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static inline void ivpu_hw_ipc_tx_set(struct ivpu_device *vdev, u32 vpu_addr)
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{
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ivpu_hw_ip_ipc_tx_set(vdev, vpu_addr);
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}
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static inline void ivpu_hw_db_set(struct ivpu_device *vdev, u32 db_id)
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{
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ivpu_hw_ip_db_set(vdev, db_id);
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}
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static inline u32 ivpu_hw_ipc_rx_addr_get(struct ivpu_device *vdev)
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{
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return ivpu_hw_ip_ipc_rx_addr_get(vdev);
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}
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static inline u32 ivpu_hw_ipc_rx_count_get(struct ivpu_device *vdev)
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{
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return ivpu_hw_ip_ipc_rx_count_get(vdev);
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}
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#endif /* __IVPU_HW_H__ */
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