dfea953ae2
According to hardware design, mem bit must be clear before entering DSM mode, as ARM core will be power gated in DSM mode. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
77 lines
1.7 KiB
C
77 lines
1.7 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/cpuidle.h>
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#include <linux/module.h>
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#include <asm/cpuidle.h>
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#include <asm/proc-fns.h>
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#include "common.h"
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#include "cpuidle.h"
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#include "hardware.h"
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static atomic_t master = ATOMIC_INIT(0);
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static DEFINE_SPINLOCK(master_lock);
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static int imx6q_enter_wait(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index)
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{
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if (atomic_inc_return(&master) == num_online_cpus()) {
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/*
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* With this lock, we prevent other cpu to exit and enter
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* this function again and become the master.
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*/
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if (!spin_trylock(&master_lock))
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goto idle;
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imx6q_set_lpm(WAIT_UNCLOCKED);
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cpu_do_idle();
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imx6q_set_lpm(WAIT_CLOCKED);
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spin_unlock(&master_lock);
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goto done;
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}
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idle:
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cpu_do_idle();
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done:
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atomic_dec(&master);
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return index;
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}
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static struct cpuidle_driver imx6q_cpuidle_driver = {
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.name = "imx6q_cpuidle",
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.owner = THIS_MODULE,
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.states = {
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/* WFI */
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ARM_CPUIDLE_WFI_STATE,
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/* WAIT */
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{
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.exit_latency = 50,
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.target_residency = 75,
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.flags = CPUIDLE_FLAG_TIME_VALID |
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CPUIDLE_FLAG_TIMER_STOP,
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.enter = imx6q_enter_wait,
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.name = "WAIT",
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.desc = "Clock off",
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},
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},
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.state_count = 2,
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.safe_state_index = 0,
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};
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int __init imx6q_cpuidle_init(void)
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{
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/* Need to enable SCU standby for entering WAIT modes */
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if (!cpu_is_imx6sx())
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imx_scu_standby_enable();
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/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
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imx6q_set_int_mem_clk_lpm(true);
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return cpuidle_register(&imx6q_cpuidle_driver, NULL);
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}
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