Philippe Bergheaud 87db7579eb ocxl: control via sysfs whether the FPGA is reloaded on a link reset ... Some opencapi FPGA images allow to control if the FPGA should be reloaded on the next adapter reset. If it is supported, the image specifies it through a Vendor Specific DVSEC in the config space of function 0. Signed-off-by: Philippe Bergheaud <felix@linux.ibm.com> Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com> Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20200619140439.153962-1-fbarrat@linux.ibm.com		2020-07-15 11:07:19 +10:00
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altera.h
cxl-base.h
cxl.h
cxllib.h
ocxl-config.h	ocxl: control via sysfs whether the FPGA is reloaded on a link reset	2020-07-15 11:07:19 +10:00
ocxl.h