Andrew Bresticker a47eb351d2 CLK: Pistachio: Register external clock gates ... Register the clock gates for the external audio and ethernet reference clocks provided by the top-level general control block. Signed-off-by: Damien Horsley <Damien.Horsley@imgtec.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: devicetree@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com> Cc: James Hartley <james.hartley@imgtec.com> Cc: James Hogan <james.hogan@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Patchwork: https://patchwork.linux-mips.org/patch/9321/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-03-31 11:59:31 +02:00
..
at91	clk: at91: implement suspend/resume for the PMC irqchip	2015-03-04 22:11:17 +01:00
bcm	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
berlin	clk: berlin: bg2q: remove non-exist "smemc" gate clock	2015-01-13 10:58:43 -08:00
hisilicon	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
keystone
mmp	clk: Add rate constraints to clocks	2015-02-02 14:23:42 -08:00
mvebu
mxs	Revert "clk: mxs: Fix invalid 32-bit access to frac registers"	2015-02-18 10:13:26 -08:00
pistachio	CLK: Pistachio: Register external clock gates	2015-03-31 11:59:31 +02:00
pxa	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
qcom	clk: qcom: fix platform_no_drv_owner.cocci warnings	2015-02-25 12:14:35 -08:00
rockchip	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
samsung	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
shmobile	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
sirf
socfpga
spear
st	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
sunxi	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
tegra	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
ti	clk: ti: Fix FAPLL parent enable bit handling	2015-02-25 12:06:29 -08:00
ux500	clk: ux500: Drop use of clk-private.h	2015-01-27 11:56:33 -08:00
versatile
x86
zynq	clk: zynq: Force CPU_2X clock to be ungated	2015-01-27 17:00:24 -08:00
clk-asm9260.c	ARM: clk: add clk-asm9260 driver	2015-01-20 10:10:51 -08:00
clk-axi-clkgen.c
clk-axm5516.c
clk-bcm2835.c
clk-cdce706.c	clk: TI CDCE706 clock synthesizer driver	2015-01-17 13:52:40 -08:00
clk-clps711x.c
clk-composite.c	clk: Replace explicit clk assignment with __clk_hw_set_clk	2015-02-18 09:40:11 -08:00
clk-conf.c
clk-devres.c
clk-divider.c	clk: divider: fix calculation of initial best divider when rounding to closest	2015-03-09 14:20:17 -07:00
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c	clk-gate: fix bit # check in clk_register_gate()	2015-01-20 10:09:05 -08:00
clk-gpio-gate.c
clk-highbank.c
clk-ls1x.c
clk-max-gen.c
clk-max-gen.h
clk-max77686.c
clk-max77802.c
clk-moxart.c
clk-mux.c	clk: Add clk_unregister_{divider, gate, mux} to close memory leak	2015-01-17 13:52:41 -08:00
clk-nomadik.c
clk-nspire.c
clk-palmas.c
clk-qoriq.c	clk: qoriq: Add support for the platform PLL	2015-02-18 09:56:43 -08:00
clk-rk808.c
clk-s2mps11.c	Please consider pulling the clk framework changes toward 3.19. It is	2014-12-20 16:42:36 -08:00
clk-si570.c
clk-si5351.c
clk-si5351.h
clk-twl6040.c
clk-u300.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c	clk: introduce clk_is_match	2015-03-11 15:56:59 -07:00
clk.h	clkdev: Always allocate a struct clk and call __clk_get() w/ CCF	2015-02-06 17:53:20 -08:00
clkdev.c	clkdev: Always allocate a struct clk and call __clk_get() w/ CCF	2015-02-06 17:53:20 -08:00
Kconfig	The clock framework changes for 3.20 contain the usual driver additions,	2015-02-21 12:30:30 -08:00
Makefile	CLK: Add basic infrastructure for Pistachio clocks	2015-03-31 11:58:56 +02:00