9d9cc58aff
The PLL of X1830 Soc from Ingenic has been greatly changed, the bypass control is placed in another register, so now two registers may needed to control the PLL. To this end, a new "bypass_reg" was introduced. In addition, when calculating rate, the PLL of X1830 introduced an extra 2x multiplier, so a new "rate_multiplier" was introduced. And adjust the code in jz47xx-cgu.c and x1000-cgu.c, make it to be compatible with the new cgu code. Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> Reviewed-by: Paul Cercueil <paul@crapouillou.net> Link: https://lkml.kernel.org/r/20200528031549.13846-3-zhouyanjie@wanyeetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> |
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| .. | ||
| cgu.c | ||
| cgu.h | ||
| jz4725b-cgu.c | ||
| jz4740-cgu.c | ||
| jz4770-cgu.c | ||
| jz4780-cgu.c | ||
| Kconfig | ||
| Makefile | ||
| pm.c | ||
| pm.h | ||
| tcu.c | ||
| x1000-cgu.c | ||