fb5d11524e
This patch adds mic support to the lpass driver, most of the driver is reused as it is, only the register level access is changed depending on te direction of the stream. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by: Kenneth Westfield <kwestfie@codeaurora.org> Signed-off-by: Mark Brown <broonie@kernel.org>
588 lines
15 KiB
C
588 lines
15 KiB
C
/*
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* Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* lpass-cpu.c -- ALSA SoC CPU DAI driver for QTi LPASS
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*/
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <linux/regmap.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include "lpass-lpaif-reg.h"
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#include "lpass.h"
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static int lpass_cpu_daiops_set_sysclk(struct snd_soc_dai *dai, int clk_id,
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unsigned int freq, int dir)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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int ret;
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if (IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id]))
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return 0;
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ret = clk_set_rate(drvdata->mi2s_osr_clk[dai->driver->id], freq);
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if (ret)
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dev_err(dai->dev, "%s() error setting mi2s osrclk to %u: %d\n",
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__func__, freq, ret);
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return ret;
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}
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static int lpass_cpu_daiops_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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int ret;
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if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id])) {
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ret = clk_prepare_enable(
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drvdata->mi2s_osr_clk[dai->driver->id]);
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if (ret) {
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dev_err(dai->dev, "%s() error in enabling mi2s osr clk: %d\n",
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__func__, ret);
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return ret;
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}
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}
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ret = clk_prepare_enable(drvdata->mi2s_bit_clk[dai->driver->id]);
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if (ret) {
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dev_err(dai->dev, "%s() error in enabling mi2s bit clk: %d\n",
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__func__, ret);
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if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id]))
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clk_disable_unprepare(
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drvdata->mi2s_osr_clk[dai->driver->id]);
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return ret;
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}
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return 0;
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}
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static void lpass_cpu_daiops_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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clk_disable_unprepare(drvdata->mi2s_bit_clk[dai->driver->id]);
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if (!IS_ERR(drvdata->mi2s_osr_clk[dai->driver->id]))
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clk_disable_unprepare(drvdata->mi2s_osr_clk[dai->driver->id]);
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}
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static int lpass_cpu_daiops_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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snd_pcm_format_t format = params_format(params);
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unsigned int channels = params_channels(params);
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unsigned int rate = params_rate(params);
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unsigned int regval;
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int bitwidth, ret;
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bitwidth = snd_pcm_format_width(format);
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if (bitwidth < 0) {
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dev_err(dai->dev, "%s() invalid bit width given: %d\n",
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__func__, bitwidth);
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return bitwidth;
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}
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regval = LPAIF_I2SCTL_LOOPBACK_DISABLE |
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LPAIF_I2SCTL_WSSRC_INTERNAL;
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switch (bitwidth) {
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case 16:
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regval |= LPAIF_I2SCTL_BITWIDTH_16;
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break;
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case 24:
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regval |= LPAIF_I2SCTL_BITWIDTH_24;
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break;
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case 32:
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regval |= LPAIF_I2SCTL_BITWIDTH_32;
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break;
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default:
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dev_err(dai->dev, "%s() invalid bitwidth given: %d\n",
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__func__, bitwidth);
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (channels) {
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case 1:
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regval |= LPAIF_I2SCTL_SPKMODE_SD0;
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regval |= LPAIF_I2SCTL_SPKMONO_MONO;
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break;
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case 2:
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regval |= LPAIF_I2SCTL_SPKMODE_SD0;
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regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
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break;
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case 4:
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regval |= LPAIF_I2SCTL_SPKMODE_QUAD01;
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regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
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break;
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case 6:
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regval |= LPAIF_I2SCTL_SPKMODE_6CH;
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regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
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break;
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case 8:
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regval |= LPAIF_I2SCTL_SPKMODE_8CH;
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regval |= LPAIF_I2SCTL_SPKMONO_STEREO;
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break;
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default:
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dev_err(dai->dev, "%s() invalid channels given: %u\n",
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__func__, channels);
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return -EINVAL;
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}
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} else {
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switch (channels) {
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case 1:
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regval |= LPAIF_I2SCTL_MICMODE_SD0;
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regval |= LPAIF_I2SCTL_MICMONO_MONO;
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break;
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case 2:
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regval |= LPAIF_I2SCTL_MICMODE_SD0;
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regval |= LPAIF_I2SCTL_MICMONO_STEREO;
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break;
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case 4:
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regval |= LPAIF_I2SCTL_MICMODE_QUAD01;
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regval |= LPAIF_I2SCTL_MICMONO_STEREO;
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break;
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case 6:
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regval |= LPAIF_I2SCTL_MICMODE_6CH;
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regval |= LPAIF_I2SCTL_MICMONO_STEREO;
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break;
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case 8:
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regval |= LPAIF_I2SCTL_MICMODE_8CH;
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regval |= LPAIF_I2SCTL_MICMONO_STEREO;
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break;
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default:
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dev_err(dai->dev, "%s() invalid channels given: %u\n",
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__func__, channels);
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return -EINVAL;
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}
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}
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
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regval);
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if (ret) {
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dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
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__func__, ret);
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return ret;
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}
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ret = clk_set_rate(drvdata->mi2s_bit_clk[dai->driver->id],
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rate * bitwidth * 2);
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if (ret) {
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dev_err(dai->dev, "%s() error setting mi2s bitclk to %u: %d\n",
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__func__, rate * bitwidth * 2, ret);
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return ret;
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}
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return 0;
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}
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static int lpass_cpu_daiops_hw_free(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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int ret;
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
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0);
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if (ret)
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dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
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__func__, ret);
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return ret;
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}
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static int lpass_cpu_daiops_prepare(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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int ret;
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unsigned int val, mask;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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val = LPAIF_I2SCTL_SPKEN_ENABLE;
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mask = LPAIF_I2SCTL_SPKEN_MASK;
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} else {
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val = LPAIF_I2SCTL_MICEN_ENABLE;
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mask = LPAIF_I2SCTL_MICEN_MASK;
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}
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id),
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mask, val);
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if (ret)
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dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
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__func__, ret);
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return ret;
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}
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static int lpass_cpu_daiops_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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int ret = -EINVAL;
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unsigned int val, mask;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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val = LPAIF_I2SCTL_SPKEN_ENABLE;
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mask = LPAIF_I2SCTL_SPKEN_MASK;
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} else {
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val = LPAIF_I2SCTL_MICEN_ENABLE;
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mask = LPAIF_I2SCTL_MICEN_MASK;
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}
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_I2SCTL_REG(drvdata->variant,
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dai->driver->id),
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mask, val);
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if (ret)
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dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
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__func__, ret);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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val = LPAIF_I2SCTL_SPKEN_DISABLE;
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mask = LPAIF_I2SCTL_SPKEN_MASK;
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} else {
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val = LPAIF_I2SCTL_MICEN_DISABLE;
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mask = LPAIF_I2SCTL_MICEN_MASK;
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}
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ret = regmap_update_bits(drvdata->lpaif_map,
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LPAIF_I2SCTL_REG(drvdata->variant,
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dai->driver->id),
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mask, val);
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if (ret)
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dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
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__func__, ret);
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break;
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}
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return ret;
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}
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const struct snd_soc_dai_ops asoc_qcom_lpass_cpu_dai_ops = {
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.set_sysclk = lpass_cpu_daiops_set_sysclk,
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.startup = lpass_cpu_daiops_startup,
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.shutdown = lpass_cpu_daiops_shutdown,
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.hw_params = lpass_cpu_daiops_hw_params,
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.hw_free = lpass_cpu_daiops_hw_free,
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.prepare = lpass_cpu_daiops_prepare,
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.trigger = lpass_cpu_daiops_trigger,
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};
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EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_ops);
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int asoc_qcom_lpass_cpu_dai_probe(struct snd_soc_dai *dai)
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{
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struct lpass_data *drvdata = snd_soc_dai_get_drvdata(dai);
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int ret;
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/* ensure audio hardware is disabled */
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ret = regmap_write(drvdata->lpaif_map,
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LPAIF_I2SCTL_REG(drvdata->variant, dai->driver->id), 0);
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if (ret)
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dev_err(dai->dev, "%s() error writing to i2sctl reg: %d\n",
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__func__, ret);
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return ret;
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}
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EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_dai_probe);
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static const struct snd_soc_component_driver lpass_cpu_comp_driver = {
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.name = "lpass-cpu",
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};
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static bool lpass_cpu_regmap_writeable(struct device *dev, unsigned int reg)
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{
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struct lpass_data *drvdata = dev_get_drvdata(dev);
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struct lpass_variant *v = drvdata->variant;
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int i;
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for (i = 0; i < v->i2s_ports; ++i)
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if (reg == LPAIF_I2SCTL_REG(v, i))
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return true;
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for (i = 0; i < v->irq_ports; ++i) {
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if (reg == LPAIF_IRQEN_REG(v, i))
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return true;
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if (reg == LPAIF_IRQCLEAR_REG(v, i))
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return true;
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}
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for (i = 0; i < v->rdma_channels; ++i) {
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if (reg == LPAIF_RDMACTL_REG(v, i))
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return true;
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if (reg == LPAIF_RDMABASE_REG(v, i))
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return true;
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if (reg == LPAIF_RDMABUFF_REG(v, i))
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return true;
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if (reg == LPAIF_RDMAPER_REG(v, i))
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return true;
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}
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for (i = 0; i < v->wrdma_channels; ++i) {
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if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
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return true;
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if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
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return true;
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if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
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return true;
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if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
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return true;
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}
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return false;
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}
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static bool lpass_cpu_regmap_readable(struct device *dev, unsigned int reg)
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{
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struct lpass_data *drvdata = dev_get_drvdata(dev);
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struct lpass_variant *v = drvdata->variant;
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int i;
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for (i = 0; i < v->i2s_ports; ++i)
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if (reg == LPAIF_I2SCTL_REG(v, i))
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return true;
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for (i = 0; i < v->irq_ports; ++i) {
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if (reg == LPAIF_IRQEN_REG(v, i))
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return true;
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if (reg == LPAIF_IRQSTAT_REG(v, i))
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return true;
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}
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for (i = 0; i < v->rdma_channels; ++i) {
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if (reg == LPAIF_RDMACTL_REG(v, i))
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return true;
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if (reg == LPAIF_RDMABASE_REG(v, i))
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return true;
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if (reg == LPAIF_RDMABUFF_REG(v, i))
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return true;
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if (reg == LPAIF_RDMACURR_REG(v, i))
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return true;
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if (reg == LPAIF_RDMAPER_REG(v, i))
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return true;
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}
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for (i = 0; i < v->wrdma_channels; ++i) {
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if (reg == LPAIF_WRDMACTL_REG(v, i + v->wrdma_channel_start))
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return true;
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if (reg == LPAIF_WRDMABASE_REG(v, i + v->wrdma_channel_start))
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return true;
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if (reg == LPAIF_WRDMABUFF_REG(v, i + v->wrdma_channel_start))
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return true;
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if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
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return true;
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if (reg == LPAIF_WRDMAPER_REG(v, i + v->wrdma_channel_start))
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return true;
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}
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return false;
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}
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static bool lpass_cpu_regmap_volatile(struct device *dev, unsigned int reg)
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{
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struct lpass_data *drvdata = dev_get_drvdata(dev);
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struct lpass_variant *v = drvdata->variant;
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int i;
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for (i = 0; i < v->irq_ports; ++i)
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if (reg == LPAIF_IRQSTAT_REG(v, i))
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return true;
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for (i = 0; i < v->rdma_channels; ++i)
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if (reg == LPAIF_RDMACURR_REG(v, i))
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return true;
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for (i = 0; i < v->wrdma_channels; ++i)
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if (reg == LPAIF_WRDMACURR_REG(v, i + v->wrdma_channel_start))
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return true;
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return false;
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}
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static struct regmap_config lpass_cpu_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.writeable_reg = lpass_cpu_regmap_writeable,
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.readable_reg = lpass_cpu_regmap_readable,
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.volatile_reg = lpass_cpu_regmap_volatile,
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.cache_type = REGCACHE_FLAT,
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};
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int asoc_qcom_lpass_cpu_platform_probe(struct platform_device *pdev)
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{
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struct lpass_data *drvdata;
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struct device_node *dsp_of_node;
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struct resource *res;
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struct lpass_variant *variant;
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struct device *dev = &pdev->dev;
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const struct of_device_id *match;
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char clk_name[16];
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int ret, i, dai_id;
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dsp_of_node = of_parse_phandle(pdev->dev.of_node, "qcom,adsp", 0);
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if (dsp_of_node) {
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dev_err(&pdev->dev, "%s() DSP exists and holds audio resources\n",
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__func__);
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return -EBUSY;
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}
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drvdata = devm_kzalloc(&pdev->dev, sizeof(struct lpass_data),
|
|
GFP_KERNEL);
|
|
if (!drvdata)
|
|
return -ENOMEM;
|
|
platform_set_drvdata(pdev, drvdata);
|
|
|
|
match = of_match_device(dev->driver->of_match_table, dev);
|
|
if (!match || !match->data)
|
|
return -EINVAL;
|
|
|
|
drvdata->variant = (struct lpass_variant *)match->data;
|
|
variant = drvdata->variant;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lpass-lpaif");
|
|
|
|
drvdata->lpaif = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR((void const __force *)drvdata->lpaif)) {
|
|
dev_err(&pdev->dev, "%s() error mapping reg resource: %ld\n",
|
|
__func__,
|
|
PTR_ERR((void const __force *)drvdata->lpaif));
|
|
return PTR_ERR((void const __force *)drvdata->lpaif);
|
|
}
|
|
|
|
lpass_cpu_regmap_config.max_register = LPAIF_WRDMAPER_REG(variant,
|
|
variant->wrdma_channels +
|
|
variant->wrdma_channel_start);
|
|
|
|
drvdata->lpaif_map = devm_regmap_init_mmio(&pdev->dev, drvdata->lpaif,
|
|
&lpass_cpu_regmap_config);
|
|
if (IS_ERR(drvdata->lpaif_map)) {
|
|
dev_err(&pdev->dev, "%s() error initializing regmap: %ld\n",
|
|
__func__, PTR_ERR(drvdata->lpaif_map));
|
|
return PTR_ERR(drvdata->lpaif_map);
|
|
}
|
|
|
|
if (variant->init)
|
|
variant->init(pdev);
|
|
|
|
for (i = 0; i < variant->num_dai; i++) {
|
|
dai_id = variant->dai_driver[i].id;
|
|
if (variant->num_dai > 1)
|
|
sprintf(clk_name, "mi2s-osr-clk%d", i);
|
|
else
|
|
sprintf(clk_name, "mi2s-osr-clk");
|
|
|
|
drvdata->mi2s_osr_clk[dai_id] = devm_clk_get(&pdev->dev,
|
|
clk_name);
|
|
if (IS_ERR(drvdata->mi2s_osr_clk[dai_id])) {
|
|
dev_warn(&pdev->dev,
|
|
"%s() error getting mi2s-osr-clk: %ld\n",
|
|
__func__,
|
|
PTR_ERR(drvdata->mi2s_osr_clk[dai_id]));
|
|
}
|
|
|
|
if (variant->num_dai > 1)
|
|
sprintf(clk_name, "mi2s-bit-clk%d", i);
|
|
else
|
|
sprintf(clk_name, "mi2s-bit-clk");
|
|
|
|
drvdata->mi2s_bit_clk[dai_id] = devm_clk_get(&pdev->dev,
|
|
clk_name);
|
|
if (IS_ERR(drvdata->mi2s_bit_clk[dai_id])) {
|
|
dev_err(&pdev->dev,
|
|
"%s() error getting mi2s-bit-clk: %ld\n",
|
|
__func__,
|
|
PTR_ERR(drvdata->mi2s_bit_clk[dai_id]));
|
|
return PTR_ERR(drvdata->mi2s_bit_clk[dai_id]);
|
|
}
|
|
}
|
|
|
|
drvdata->ahbix_clk = devm_clk_get(&pdev->dev, "ahbix-clk");
|
|
if (IS_ERR(drvdata->ahbix_clk)) {
|
|
dev_err(&pdev->dev, "%s() error getting ahbix-clk: %ld\n",
|
|
__func__, PTR_ERR(drvdata->ahbix_clk));
|
|
return PTR_ERR(drvdata->ahbix_clk);
|
|
}
|
|
|
|
ret = clk_set_rate(drvdata->ahbix_clk, LPASS_AHBIX_CLOCK_FREQUENCY);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "%s() error setting rate on ahbix_clk: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
dev_dbg(&pdev->dev, "%s() set ahbix_clk rate to %lu\n", __func__,
|
|
clk_get_rate(drvdata->ahbix_clk));
|
|
|
|
ret = clk_prepare_enable(drvdata->ahbix_clk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "%s() error enabling ahbix_clk: %d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = devm_snd_soc_register_component(&pdev->dev,
|
|
&lpass_cpu_comp_driver,
|
|
variant->dai_driver,
|
|
variant->num_dai);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "%s() error registering cpu driver: %d\n",
|
|
__func__, ret);
|
|
goto err_clk;
|
|
}
|
|
|
|
ret = asoc_qcom_lpass_platform_register(pdev);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "%s() error registering platform driver: %d\n",
|
|
__func__, ret);
|
|
goto err_clk;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_clk:
|
|
clk_disable_unprepare(drvdata->ahbix_clk);
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_probe);
|
|
|
|
int asoc_qcom_lpass_cpu_platform_remove(struct platform_device *pdev)
|
|
{
|
|
struct lpass_data *drvdata = platform_get_drvdata(pdev);
|
|
|
|
if (drvdata->variant->exit)
|
|
drvdata->variant->exit(pdev);
|
|
|
|
clk_disable_unprepare(drvdata->ahbix_clk);
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(asoc_qcom_lpass_cpu_platform_remove);
|