c7ed1ab3f7
This fixes up some of the I/D/F clock ambiguity in the sh-sci driver. The interface clock in most cases just wraps back to the peripheral clock, while the function clock wraps in to the MSTP bits. As the logic was somewhat inverted, this cleans that up, and also enables all CPUs with SCI MSTP bits to match function clocks through clkdev lookup. As a result, this gets rid of the clk string abuse on the sh side, and the clock string will be killed off once the ARM code has had a chance to sync up. This also enables MSTP gating on CPUs like 7786 which had never wired it up before. Impacted CPUs are primarily all SH-Mobiles, SH7785, and SH7786. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
752 lines
18 KiB
C
752 lines
18 KiB
C
/*
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* SH7722 Setup
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*
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* Copyright (C) 2006 - 2008 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_timer.h>
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#include <linux/uio_driver.h>
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#include <linux/usb/m66592.h>
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#include <asm/clock.h>
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#include <asm/dmaengine.h>
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#include <asm/mmzone.h>
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#include <asm/siu.h>
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#include <cpu/dma-register.h>
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#include <cpu/sh7722.h>
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static struct sh_dmae_slave_config sh7722_dmae_slaves[] = {
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{
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.slave_id = SHDMA_SLAVE_SCIF0_TX,
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.addr = 0xffe0000c,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x21,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF0_RX,
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.addr = 0xffe00014,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x22,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_TX,
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.addr = 0xffe1000c,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x25,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF1_RX,
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.addr = 0xffe10014,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x26,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_TX,
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.addr = 0xffe2000c,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x29,
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}, {
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.slave_id = SHDMA_SLAVE_SCIF2_RX,
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.addr = 0xffe20014,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
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.mid_rid = 0x2a,
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}, {
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.slave_id = SHDMA_SLAVE_SIUA_TX,
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.addr = 0xa454c098,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
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.mid_rid = 0xb1,
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}, {
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.slave_id = SHDMA_SLAVE_SIUA_RX,
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.addr = 0xa454c090,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
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.mid_rid = 0xb2,
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}, {
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.slave_id = SHDMA_SLAVE_SIUB_TX,
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.addr = 0xa454c09c,
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.chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
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.mid_rid = 0xb5,
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}, {
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.slave_id = SHDMA_SLAVE_SIUB_RX,
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.addr = 0xa454c094,
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.chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
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.mid_rid = 0xb6,
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},
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};
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static struct sh_dmae_channel sh7722_dmae_channels[] = {
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{
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.offset = 0,
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.dmars = 0,
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.dmars_bit = 0,
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}, {
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.offset = 0x10,
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.dmars = 0,
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.dmars_bit = 8,
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}, {
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.offset = 0x20,
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.dmars = 4,
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.dmars_bit = 0,
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}, {
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.offset = 0x30,
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.dmars = 4,
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.dmars_bit = 8,
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}, {
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.offset = 0x50,
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.dmars = 8,
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.dmars_bit = 0,
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}, {
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.offset = 0x60,
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.dmars = 8,
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.dmars_bit = 8,
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}
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};
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static unsigned int ts_shift[] = TS_SHIFT;
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static struct sh_dmae_pdata dma_platform_data = {
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.slave = sh7722_dmae_slaves,
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.slave_num = ARRAY_SIZE(sh7722_dmae_slaves),
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.channel = sh7722_dmae_channels,
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.channel_num = ARRAY_SIZE(sh7722_dmae_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
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.ts_low_mask = CHCR_TS_LOW_MASK,
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.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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};
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static struct resource sh7722_dmae_resources[] = {
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[0] = {
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/* Channel registers and DMAOR */
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.start = 0xfe008020,
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.end = 0xfe00808f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* DMARSx */
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.start = 0xfe009000,
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.end = 0xfe00900b,
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.flags = IORESOURCE_MEM,
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},
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{
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/* DMA error IRQ */
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.start = 78,
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.end = 78,
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 0-3 */
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.start = 48,
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.end = 51,
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.flags = IORESOURCE_IRQ,
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},
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{
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/* IRQ for channels 4-5 */
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.start = 76,
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.end = 77,
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.flags = IORESOURCE_IRQ,
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},
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};
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struct platform_device dma_device = {
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.name = "sh-dma-engine",
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.id = -1,
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.resource = sh7722_dmae_resources,
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.num_resources = ARRAY_SIZE(sh7722_dmae_resources),
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.dev = {
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.platform_data = &dma_platform_data,
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},
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.archdata = {
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.hwblk_id = HWBLK_DMAC,
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},
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};
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/* Serial */
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xffe00000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 80, 80, 80, 80 },
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xffe10000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 81, 81, 81, 81 },
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct plat_sci_port scif2_platform_data = {
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.mapbase = 0xffe20000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 82, 82, 82, 82 },
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};
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static struct platform_device scif2_device = {
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.name = "sh-sci",
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.id = 2,
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.dev = {
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.platform_data = &scif2_platform_data,
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},
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};
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xa465fec0,
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.end = 0xa465fec0 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Period IRQ */
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.start = 45,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* Carry IRQ */
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.start = 46,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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/* Alarm IRQ */
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.start = 44,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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.archdata = {
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.hwblk_id = HWBLK_RTC,
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},
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};
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static struct m66592_platdata usbf_platdata = {
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.on_chip = 1,
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};
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static struct resource usbf_resources[] = {
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[0] = {
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.name = "USBF",
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.start = 0x04480000,
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.end = 0x044800FF,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 65,
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.end = 65,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device usbf_device = {
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.name = "m66592_udc",
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.id = 0, /* "usbf0" clock */
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.dev = {
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.dma_mask = NULL,
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.coherent_dma_mask = 0xffffffff,
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.platform_data = &usbf_platdata,
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},
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.num_resources = ARRAY_SIZE(usbf_resources),
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.resource = usbf_resources,
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.archdata = {
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.hwblk_id = HWBLK_USBF,
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},
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};
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static struct resource iic_resources[] = {
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[0] = {
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.name = "IIC",
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.start = 0x04470000,
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.end = 0x04470017,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 96,
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.end = 99,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device iic_device = {
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.name = "i2c-sh_mobile",
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.id = 0, /* "i2c0" clock */
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.num_resources = ARRAY_SIZE(iic_resources),
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.resource = iic_resources,
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.archdata = {
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.hwblk_id = HWBLK_IIC,
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},
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};
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static struct uio_info vpu_platform_data = {
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.name = "VPU4",
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.version = "0",
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.irq = 60,
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};
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static struct resource vpu_resources[] = {
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[0] = {
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.name = "VPU",
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.start = 0xfe900000,
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.end = 0xfe9022eb,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* place holder for contiguous memory */
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},
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};
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static struct platform_device vpu_device = {
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.name = "uio_pdrv_genirq",
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.id = 0,
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.dev = {
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.platform_data = &vpu_platform_data,
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},
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.resource = vpu_resources,
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.num_resources = ARRAY_SIZE(vpu_resources),
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.archdata = {
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.hwblk_id = HWBLK_VPU,
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},
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};
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static struct uio_info veu_platform_data = {
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.name = "VEU",
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.version = "0",
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.irq = 54,
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};
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static struct resource veu_resources[] = {
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[0] = {
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.name = "VEU",
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.start = 0xfe920000,
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.end = 0xfe9200b7,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* place holder for contiguous memory */
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},
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};
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static struct platform_device veu_device = {
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.name = "uio_pdrv_genirq",
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.id = 1,
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.dev = {
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.platform_data = &veu_platform_data,
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},
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.resource = veu_resources,
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.num_resources = ARRAY_SIZE(veu_resources),
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.archdata = {
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.hwblk_id = HWBLK_VEU,
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},
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};
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static struct uio_info jpu_platform_data = {
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.name = "JPU",
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.version = "0",
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.irq = 27,
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};
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static struct resource jpu_resources[] = {
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[0] = {
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.name = "JPU",
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.start = 0xfea00000,
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.end = 0xfea102d3,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* place holder for contiguous memory */
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},
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};
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static struct platform_device jpu_device = {
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.name = "uio_pdrv_genirq",
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.id = 2,
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.dev = {
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.platform_data = &jpu_platform_data,
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},
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.resource = jpu_resources,
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.num_resources = ARRAY_SIZE(jpu_resources),
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.archdata = {
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.hwblk_id = HWBLK_JPU,
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},
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};
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static struct sh_timer_config cmt_platform_data = {
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.channel_offset = 0x60,
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.timer_bit = 5,
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.clk = "cmt0",
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.clockevent_rating = 125,
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.clocksource_rating = 125,
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};
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static struct resource cmt_resources[] = {
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[0] = {
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.start = 0x044a0060,
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.end = 0x044a006b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 104,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device cmt_device = {
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.name = "sh_cmt",
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.id = 0,
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.dev = {
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.platform_data = &cmt_platform_data,
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},
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.resource = cmt_resources,
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.num_resources = ARRAY_SIZE(cmt_resources),
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.archdata = {
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.hwblk_id = HWBLK_CMT,
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},
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};
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static struct sh_timer_config tmu0_platform_data = {
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.channel_offset = 0x04,
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.timer_bit = 0,
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.clk = "tmu0",
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.clockevent_rating = 200,
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};
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static struct resource tmu0_resources[] = {
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[0] = {
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.start = 0xffd80008,
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.end = 0xffd80013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 16,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu0_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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.archdata = {
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.hwblk_id = HWBLK_TMU,
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},
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};
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static struct sh_timer_config tmu1_platform_data = {
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clk = "tmu0",
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.clocksource_rating = 200,
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};
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static struct resource tmu1_resources[] = {
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[0] = {
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.start = 0xffd80014,
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.end = 0xffd8001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 17,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu1_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu1_platform_data,
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},
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.resource = tmu1_resources,
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.num_resources = ARRAY_SIZE(tmu1_resources),
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.archdata = {
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.hwblk_id = HWBLK_TMU,
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},
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};
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static struct sh_timer_config tmu2_platform_data = {
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.channel_offset = 0x1c,
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.timer_bit = 2,
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.clk = "tmu0",
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};
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static struct resource tmu2_resources[] = {
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[0] = {
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.start = 0xffd80020,
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.end = 0xffd8002b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 18,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu2_device = {
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.name = "sh_tmu",
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.id = 2,
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.dev = {
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.platform_data = &tmu2_platform_data,
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},
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.resource = tmu2_resources,
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.num_resources = ARRAY_SIZE(tmu2_resources),
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.archdata = {
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.hwblk_id = HWBLK_TMU,
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},
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};
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static struct siu_platform siu_platform_data = {
|
|
.dma_dev = &dma_device.dev,
|
|
.dma_slave_tx_a = SHDMA_SLAVE_SIUA_TX,
|
|
.dma_slave_rx_a = SHDMA_SLAVE_SIUA_RX,
|
|
.dma_slave_tx_b = SHDMA_SLAVE_SIUB_TX,
|
|
.dma_slave_rx_b = SHDMA_SLAVE_SIUB_RX,
|
|
};
|
|
|
|
static struct resource siu_resources[] = {
|
|
[0] = {
|
|
.start = 0xa4540000,
|
|
.end = 0xa454c10f,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.start = 108,
|
|
.flags = IORESOURCE_IRQ,
|
|
},
|
|
};
|
|
|
|
static struct platform_device siu_device = {
|
|
.name = "sh_siu",
|
|
.id = -1,
|
|
.dev = {
|
|
.platform_data = &siu_platform_data,
|
|
},
|
|
.resource = siu_resources,
|
|
.num_resources = ARRAY_SIZE(siu_resources),
|
|
.archdata = {
|
|
.hwblk_id = HWBLK_SIU,
|
|
},
|
|
};
|
|
|
|
static struct platform_device *sh7722_devices[] __initdata = {
|
|
&scif0_device,
|
|
&scif1_device,
|
|
&scif2_device,
|
|
&cmt_device,
|
|
&tmu0_device,
|
|
&tmu1_device,
|
|
&tmu2_device,
|
|
&rtc_device,
|
|
&usbf_device,
|
|
&iic_device,
|
|
&vpu_device,
|
|
&veu_device,
|
|
&jpu_device,
|
|
&siu_device,
|
|
&dma_device,
|
|
};
|
|
|
|
static int __init sh7722_devices_setup(void)
|
|
{
|
|
platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
|
|
platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
|
|
platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
|
|
|
|
return platform_add_devices(sh7722_devices,
|
|
ARRAY_SIZE(sh7722_devices));
|
|
}
|
|
arch_initcall(sh7722_devices_setup);
|
|
|
|
static struct platform_device *sh7722_early_devices[] __initdata = {
|
|
&scif0_device,
|
|
&scif1_device,
|
|
&scif2_device,
|
|
&cmt_device,
|
|
&tmu0_device,
|
|
&tmu1_device,
|
|
&tmu2_device,
|
|
};
|
|
|
|
void __init plat_early_device_setup(void)
|
|
{
|
|
early_platform_add_devices(sh7722_early_devices,
|
|
ARRAY_SIZE(sh7722_early_devices));
|
|
}
|
|
|
|
enum {
|
|
UNUSED=0,
|
|
ENABLED,
|
|
DISABLED,
|
|
|
|
/* interrupt sources */
|
|
IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
|
|
HUDI,
|
|
SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
|
|
RTC_ATI, RTC_PRI, RTC_CUI,
|
|
DMAC0, DMAC1, DMAC2, DMAC3,
|
|
VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
|
|
VPU, TPU,
|
|
USB_USBI0, USB_USBI1,
|
|
DMAC4, DMAC5, DMAC_DADERR,
|
|
KEYSC,
|
|
SCIF0, SCIF1, SCIF2, SIOF0, SIOF1, SIO,
|
|
FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
|
|
I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
|
|
CMT, TSIF, SIU, TWODG,
|
|
TMU0, TMU1, TMU2,
|
|
IRDA, JPU, LCDC,
|
|
|
|
/* interrupt groups */
|
|
SIM, RTC, DMAC0123, VIOVOU, USB, DMAC45, FLCTL, I2C, SDHI,
|
|
};
|
|
|
|
static struct intc_vect vectors[] __initdata = {
|
|
INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
|
|
INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
|
|
INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
|
|
INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
|
|
INTC_VECT(SIM_ERI, 0x700), INTC_VECT(SIM_RXI, 0x720),
|
|
INTC_VECT(SIM_TXI, 0x740), INTC_VECT(SIM_TEI, 0x760),
|
|
INTC_VECT(RTC_ATI, 0x780), INTC_VECT(RTC_PRI, 0x7a0),
|
|
INTC_VECT(RTC_CUI, 0x7c0),
|
|
INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
|
|
INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
|
|
INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
|
|
INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
|
|
INTC_VECT(VPU, 0x980), INTC_VECT(TPU, 0x9a0),
|
|
INTC_VECT(USB_USBI0, 0xa20), INTC_VECT(USB_USBI1, 0xa40),
|
|
INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
|
|
INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
|
|
INTC_VECT(SCIF0, 0xc00), INTC_VECT(SCIF1, 0xc20),
|
|
INTC_VECT(SCIF2, 0xc40), INTC_VECT(SIOF0, 0xc80),
|
|
INTC_VECT(SIOF1, 0xca0), INTC_VECT(SIO, 0xd00),
|
|
INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
|
|
INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
|
|
INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
|
|
INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
|
|
INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
|
|
INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
|
|
INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
|
|
INTC_VECT(SIU, 0xf80), INTC_VECT(TWODG, 0xfa0),
|
|
INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
|
|
INTC_VECT(TMU2, 0x440), INTC_VECT(IRDA, 0x480),
|
|
INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
|
|
};
|
|
|
|
static struct intc_group groups[] __initdata = {
|
|
INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI),
|
|
INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
|
|
INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
|
|
INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
|
|
INTC_GROUP(USB, USB_USBI0, USB_USBI1),
|
|
INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
|
|
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
|
|
FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
|
|
INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
|
|
};
|
|
|
|
static struct intc_mask_reg mask_registers[] __initdata = {
|
|
{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
|
|
{ } },
|
|
{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
|
|
{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
|
|
{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
|
|
{ 0, 0, 0, VPU, } },
|
|
{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
|
|
{ SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
|
|
{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
|
|
{ 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
|
|
{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
|
|
{ KEYSC, DMAC_DADERR, DMAC5, DMAC4, 0, SCIF2, SCIF1, SCIF0 } },
|
|
{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
|
|
{ 0, 0, 0, SIO, 0, 0, SIOF1, SIOF0 } },
|
|
{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
|
|
{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
|
|
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
|
|
{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
|
|
{ DISABLED, DISABLED, ENABLED, ENABLED, 0, 0, TWODG, SIU } },
|
|
{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
|
|
{ 0, 0, 0, CMT, 0, USB_USBI1, USB_USBI0, } },
|
|
{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
|
|
{ } },
|
|
{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
|
|
{ 0, RTC_CUI, RTC_PRI, RTC_ATI, 0, TPU, 0, TSIF } },
|
|
{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
|
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static struct intc_prio_reg prio_registers[] __initdata = {
|
|
{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, IRDA } },
|
|
{ 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
|
|
{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
|
|
{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
|
|
{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, 0, VPU } },
|
|
{ 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
|
|
{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, SCIF2 } },
|
|
{ 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C } },
|
|
{ 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, RTC } },
|
|
{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
|
|
{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, 0, 0, SDHI } },
|
|
{ 0xa408002c, 0, 16, 4, /* IPRL */ { TWODG, 0, TPU } },
|
|
{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
|
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static struct intc_sense_reg sense_registers[] __initdata = {
|
|
{ 0xa414001c, 16, 2, /* ICR1 */
|
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static struct intc_mask_reg ack_registers[] __initdata = {
|
|
{ 0xa4140024, 0, 8, /* INTREQ00 */
|
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static struct intc_desc intc_desc __initdata = {
|
|
.name = "sh7722",
|
|
.force_enable = ENABLED,
|
|
.force_disable = DISABLED,
|
|
.hw = INTC_HW_DESC(vectors, groups, mask_registers,
|
|
prio_registers, sense_registers, ack_registers),
|
|
};
|
|
|
|
void __init plat_irq_setup(void)
|
|
{
|
|
register_intc_controller(&intc_desc);
|
|
}
|
|
|
|
void __init plat_mem_setup(void)
|
|
{
|
|
/* Register the URAM space as Node 1 */
|
|
setup_bootmem_node(1, 0x055f0000, 0x05610000);
|
|
}
|