b7f817547d
Utilize new split between board & SoC, and new SoC device trees split into pre & post utilizing 'template' includes for SoC IP blocks. Other changes include: * Moved to a standard 2 #address-cells & #size-cells at top-level * Moved to specifying interrupt-parent for mpic at root * Moved to 4-cell mpic interrupt cells to support MPIC timers * Removed CPU properties setup by u-boot to match other .dts * Added localbus node, but no chipselect details at this point * Reworked PCIe nodes to allow supportin IRQs for controller (errors) and moved PCI device IRQs down to virtual bridge level * Moved mdio nodes up one level instead of under tsec nodes * Updated ethernet 'model' to 'eTSEC' as that's what on MPC8544 * Dropping "fsl,mpc8544-IP..." from compatibles for standard blocks Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
105 lines
2.6 KiB
Text
105 lines
2.6 KiB
Text
/*
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* MPC8544 DS Device Tree Source
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*
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* Copyright 2007, 2008 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "fsl/mpc8544si-pre.dtsi"
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/ {
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model = "MPC8544DS";
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compatible = "MPC8544DS", "MPC85xxDS";
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memory {
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device_type = "memory";
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reg = <0 0 0 0>; // Filled by U-Boot
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};
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lbc: localbus@e0005000 {
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reg = <0 0xe0005000 0 0x1000>;
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};
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board_soc: soc: soc8544@e0000000 {
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ranges = <0x0 0x0 0xe0000000 0x100000>;
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};
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pci0: pci@e0008000 {
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reg = <0 0xe0008000 0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
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clock-frequency = <66666666>;
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x11 J17 Slot 1 */
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0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x8800 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x8800 0x0 0x0 0x3 &mpic 0x4 0x1 0 0
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0x8800 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x12 J16 Slot 2 */
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0x9000 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x9000 0x0 0x0 0x2 &mpic 0x4 0x1 0 0
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0x9000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x9000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0>;
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};
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pci1: pcie@e0009000 {
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reg = <0x0 0xe0009000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xe1010000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci2: pcie@e000a000 {
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reg = <0x0 0xe000a000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
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0x1000000 0x0 0x00000000 0 0xe1020000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x10000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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board_pci3: pci3: pcie@e000b000 {
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reg = <0x0 0xe000b000 0x0 0x1000>;
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ranges = <0x2000000 0x0 0xb0000000 0 0xb0000000 0x0 0x100000
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0x1000000 0x0 0x00000000 0 0xb0100000 0x0 0x100000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xb0000000
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0x2000000 0x0 0xb0000000
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0x0 0x100000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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/*
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* mpc8544ds.dtsi must be last to ensure board_pci3 overrides pci3 settings
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* for interrupt-map & interrupt-map-mask
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*/
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/include/ "fsl/mpc8544si-post.dtsi"
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/include/ "mpc8544ds.dtsi"
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