e32f7ec2e8
The dmtimer framework update broke 32 kHz timer as udelay() does not work before system timer is started (and GPT1 should not be reset). This also makes the GP timer use GPT1. This requires a fix in clock framework. Signed-off-by: Timo Teras <timo.teras@solidboot.com> Signed-off-by: Juha Yrjola <juha.yrjola@solidboot.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
/*
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* linux/arch/arm/mach-omap2/timer-gp.c
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*
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* OMAP2 GP timer support.
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*
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* Copyright (C) 2005 Nokia Corporation
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* Author: Paul Mundt <paul.mundt@nokia.com>
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* Juha Yrjölä <juha.yrjola@nokia.com>
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* OMAP Dual-mode timer framework support by Timo Teras
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*
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* Some parts based off of TI's 24xx code:
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*
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* Copyright (C) 2004 Texas Instruments, Inc.
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*
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* Roughly modelled after the OMAP1 MPU timer code.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/time.h>
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#include <linux/interrupt.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <asm/mach/time.h>
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#include <asm/arch/dmtimer.h>
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static struct omap_dm_timer *gptimer;
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static inline void omap2_gp_timer_start(unsigned long load_val)
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{
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omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
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omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
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omap_dm_timer_start(gptimer);
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}
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static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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write_seqlock(&xtime_lock);
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omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
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timer_tick(regs);
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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static struct irqaction omap2_gp_timer_irq = {
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.name = "gp timer",
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.flags = SA_INTERRUPT | SA_TIMER,
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.handler = omap2_gp_timer_interrupt,
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};
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static void __init omap2_gp_timer_init(void)
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{
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u32 tick_period;
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omap_dm_timer_init();
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gptimer = omap_dm_timer_request_specific(1);
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BUG_ON(gptimer == NULL);
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omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
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tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / 100;
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tick_period -= 1;
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setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
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omap2_gp_timer_start(tick_period);
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}
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struct sys_timer omap_timer = {
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.init = omap2_gp_timer_init,
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};
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