e21d2aa76e
This plugs in clkdev lookups for the SH7786 clocks and migrates off of clock string usage for the TMU clocks. Previously the TMU clocks were aliased to the peripheral clock, so this gets the driver actually toggling the proper clocks now as well. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
205 lines
5.5 KiB
C
205 lines
5.5 KiB
C
/*
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* arch/sh/kernel/cpu/sh4a/clock-sh7786.c
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*
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* SH7786 support for the clock framework
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*
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* Copyright (C) 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/clkdev.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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/*
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* Default rate for the root input clock, reset this with clk_set_rate()
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* from the platform code.
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*/
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static struct clk extal_clk = {
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.name = "extal",
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.id = -1,
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.rate = 33333333,
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};
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static unsigned long pll_recalc(struct clk *clk)
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{
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int multiplier;
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/*
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* Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
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* while modes 3, 4, and 5 use an x32.
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*/
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multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
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return clk->parent->rate * multiplier;
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}
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static struct clk_ops pll_clk_ops = {
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.recalc = pll_recalc,
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};
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static struct clk pll_clk = {
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.name = "pll_clk",
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.id = -1,
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.ops = &pll_clk_ops,
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.parent = &extal_clk,
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.flags = CLK_ENABLE_ON_INIT,
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};
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static struct clk *clks[] = {
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&extal_clk,
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&pll_clk,
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};
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static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
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24, 32, 36, 48 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = div2,
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.nr_divisors = ARRAY_SIZE(div2),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
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#define DIV4(_str, _bit, _mask, _flags) \
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SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags)
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struct clk div4_clks[DIV4_NR] = {
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[DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0),
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[DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0),
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[DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT),
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[DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT),
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[DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT),
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};
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#define MSTPCR0 0xffc40030
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#define MSTPCR1 0xffc40034
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static struct clk mstp_clks[] = {
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/* MSTPCR0 */
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SH_CLK_MSTP32("sci_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0),
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SH_CLK_MSTP32("sci_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0),
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SH_CLK_MSTP32("sci_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0),
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SH_CLK_MSTP32("sci_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0),
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SH_CLK_MSTP32("sci_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0),
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SH_CLK_MSTP32("sci_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0),
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SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0),
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SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0),
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SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0),
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SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0),
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SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0),
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SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0),
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SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0),
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SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0),
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SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0),
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SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0),
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SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0),
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SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0),
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SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0),
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SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0),
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SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0),
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/* MSTPCR1 */
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SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0),
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SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0),
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SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0),
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SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0),
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SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0),
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SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0),
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SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0),
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SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0),
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};
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static struct clk_lookup lookups[] = {
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{
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/* TMU0 */
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.dev_id = "sh_tmu.0",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[17], /* tmu012_fck */
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}, {
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/* TMU1 */
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.dev_id = "sh_tmu.1",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[17],
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}, {
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/* TMU2 */
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.dev_id = "sh_tmu.2",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[17],
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}, {
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/* TMU3 */
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.dev_id = "sh_tmu.3",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[16], /* tmu345_fck */
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}, {
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/* TMU4 */
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.dev_id = "sh_tmu.4",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[16],
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}, {
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/* TMU5 */
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.dev_id = "sh_tmu.5",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[16],
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}, {
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/* TMU6 */
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.dev_id = "sh_tmu.6",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[15], /* tmu678_fck */
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}, {
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/* TMU7 */
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.dev_id = "sh_tmu.7",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[15],
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}, {
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/* TMU8 */
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.dev_id = "sh_tmu.8",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[15],
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}, {
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/* TMU9 */
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.dev_id = "sh_tmu.9",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[14], /* tmu9_11_fck */
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}, {
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/* TMU10 */
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.dev_id = "sh_tmu.10",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[14],
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}, {
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/* TMU11 */
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.dev_id = "sh_tmu.11",
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.con_id = "tmu_fck",
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.clk = &mstp_clks[14],
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}
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};
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int __init arch_clk_init(void)
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{
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int i, ret = 0;
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for (i = 0; i < ARRAY_SIZE(clks); i++)
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ret |= clk_register(clks[i]);
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for (i = 0; i < ARRAY_SIZE(lookups); i++)
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clkdev_add(&lookups[i]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
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&div4_table);
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if (!ret)
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ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks));
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return ret;
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}
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