solutions for HLS lab2

hls/lab2/README.md

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+exercise 1: design solo PS e AXI Timer;
+exercise 2: mmult baseline
+exercise 3: mmult pipelined
+exercise 4: mmult con BRAM
+exercise 5: mmult Unrolled
+exercise 6: mmult Array Part
+exercise 7: mmult Pipeline outer
+exercise 8: mmult Pipeline outer 200MHz
+exercise 9: mmult Pipeline outer 300MHz

hls/lab2/exercise_1.tcl

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+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {1} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_2.tcl

@@ -0,0 +1,976 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_2} [current_project]
+update_ip_catalog
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:1.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:1.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_3.tcl

@@ -0,0 +1,971 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_3} [current_project]
+update_ip_catalog
+
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:2.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:2.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_4.tcl

@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_4} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:3.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:3.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_5.tcl

@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_5} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:4.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:4.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_6.tcl

@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_6} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:6.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:6.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_7.tcl

@@ -0,0 +1,975 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_7} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:hls:mmult:7.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:7.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_8.tcl

@@ -0,0 +1,989 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_8} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:ip:clk_wiz:6.0\
+xilinx.com:hls:mmult:8.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: clk_wiz_0, and set properties
+  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+  set_property -dict [ list \
+   CONFIG.CLKOUT1_JITTER {102.086} \
+   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000} \
+   CONFIG.CLK_OUT1_PORT {clk_out_200} \
+   CONFIG.MMCM_CLKOUT0_DIVIDE_F {6.000} \
+   CONFIG.RESET_PORT {resetn} \
+   CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ ] $clk_wiz_0
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:8.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_ps8_0_100M/dcm_locked]
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out_200] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk1 [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins clk_wiz_0/resetn] [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exercise_9.tcl

@@ -0,0 +1,989 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+   set script_path [file normalize [info script]]
+   set script_folder [file dirname $script_path]
+   return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2020.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+   puts ""
+   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+   return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+# If there is no project opened, this script will create a
+# project, but make sure you do not have an existing project
+# <./myproj/project_1.xpr> in the current working folder.
+
+set list_projs [get_projects -quiet]
+if { $list_projs eq "" } {
+   create_project project_1 myproj -part xczu3eg-sbva484-1-e
+   set_property BOARD_PART em.avnet.com:ultra96v2:part0:1.0 [current_project]
+}
+
+set_property  ip_repo_paths  {exported_ips/xilinx_com_hls_exercise_9} [current_project]
+update_ip_catalog
+
+# CHANGE DESIGN NAME HERE
+variable design_name
+set design_name design_1
+
+# If you do not already have an existing IP Integrator design open,
+# you can create a design using the following command:
+#    create_bd_design $design_name
+
+# Creating design if needed
+set errMsg ""
+set nRet 0
+
+set cur_design [current_bd_design -quiet]
+set list_cells [get_bd_cells -quiet]
+
+if { ${design_name} eq "" } {
+   # USE CASES:
+   #    1) Design_name not set
+
+   set errMsg "Please set the variable <design_name> to a non-empty value."
+   set nRet 1
+
+} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
+   # USE CASES:
+   #    2): Current design opened AND is empty AND names same.
+   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
+   #    4): Current design opened AND is empty AND names diff; design_name exists in project.
+
+   if { $cur_design ne $design_name } {
+      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
+      set design_name [get_property NAME $cur_design]
+   }
+   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."
+
+} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
+   # USE CASES:
+   #    5) Current design opened AND has components AND same names.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 1
+} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
+   # USE CASES: 
+   #    6) Current opened design, has components, but diff names, design_name exists in project.
+   #    7) No opened design, design_name exists in project.
+
+   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
+   set nRet 2
+
+} else {
+   # USE CASES:
+   #    8) No opened design, design_name not in project.
+   #    9) Current opened design, has components, but diff names, design_name not in project.
+
+   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
+
+   create_bd_design $design_name
+
+   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
+   current_bd_design $design_name
+
+}
+
+common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."
+
+if { $nRet != 0 } {
+   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
+   return $nRet
+}
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+   set list_check_ips "\ 
+xilinx.com:ip:axi_timer:2.0\
+xilinx.com:ip:clk_wiz:6.0\
+xilinx.com:hls:mmult:9.0\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+"
+
+   set list_ips_missing ""
+   common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+   foreach ip_vlnv $list_check_ips {
+      set ip_obj [get_ipdefs -all $ip_vlnv]
+      if { $ip_obj eq "" } {
+         lappend list_ips_missing $ip_vlnv
+      }
+   }
+
+   if { $list_ips_missing ne "" } {
+      catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+      set bCheckIPsPassed 0
+   }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+  common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+  return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+  variable script_folder
+  variable design_name
+
+  if { $parentCell eq "" } {
+     set parentCell [get_bd_cells /]
+  }
+
+  # Get object for parentCell
+  set parentObj [get_bd_cells $parentCell]
+  if { $parentObj == "" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+     return
+  }
+
+  # Make sure parentObj is hier blk
+  set parentType [get_property TYPE $parentObj]
+  if { $parentType ne "hier" } {
+     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+     return
+  }
+
+  # Save current instance; Restore later
+  set oldCurInst [current_bd_instance .]
+
+  # Set parent object as current
+  current_bd_instance $parentObj
+
+
+  # Create interface ports
+
+  # Create ports
+
+  # Create instance: axi_timer_0, and set properties
+  set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ]
+
+  # Create instance: clk_wiz_0, and set properties
+  set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ]
+  set_property -dict [ list \
+   CONFIG.CLKOUT1_JITTER {94.862} \
+   CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {300.000} \
+   CONFIG.CLK_OUT1_PORT {clk_out_300} \
+   CONFIG.MMCM_CLKOUT0_DIVIDE_F {4.000} \
+   CONFIG.RESET_PORT {resetn} \
+   CONFIG.RESET_TYPE {ACTIVE_LOW} \
+ ] $clk_wiz_0
+
+  # Create instance: mmult_0, and set properties
+  set mmult_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:mmult:9.0 mmult_0 ]
+
+  # Create instance: ps8_0_axi_periph, and set properties
+  set ps8_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps8_0_axi_periph ]
+  set_property -dict [ list \
+   CONFIG.NUM_MI {2} \
+ ] $ps8_0_axi_periph
+
+  # Create instance: rst_ps8_0_100M, and set properties
+  set rst_ps8_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps8_0_100M ]
+
+  # Create instance: zynq_ultra_ps_e_0, and set properties
+  set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+  set_property -dict [ list \
+   CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+   CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+   CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+   CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+   CONFIG.PSU_MIO_0_DIRECTION {out} \
+   CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_0_POLARITY {Default} \
+   CONFIG.PSU_MIO_10_DIRECTION {inout} \
+   CONFIG.PSU_MIO_10_POLARITY {Default} \
+   CONFIG.PSU_MIO_11_DIRECTION {inout} \
+   CONFIG.PSU_MIO_11_POLARITY {Default} \
+   CONFIG.PSU_MIO_12_DIRECTION {inout} \
+   CONFIG.PSU_MIO_12_POLARITY {Default} \
+   CONFIG.PSU_MIO_13_DIRECTION {inout} \
+   CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_13_POLARITY {Default} \
+   CONFIG.PSU_MIO_14_DIRECTION {inout} \
+   CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_14_POLARITY {Default} \
+   CONFIG.PSU_MIO_15_DIRECTION {inout} \
+   CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_15_POLARITY {Default} \
+   CONFIG.PSU_MIO_16_DIRECTION {inout} \
+   CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_16_POLARITY {Default} \
+   CONFIG.PSU_MIO_17_DIRECTION {inout} \
+   CONFIG.PSU_MIO_17_POLARITY {Default} \
+   CONFIG.PSU_MIO_18_DIRECTION {inout} \
+   CONFIG.PSU_MIO_18_POLARITY {Default} \
+   CONFIG.PSU_MIO_19_DIRECTION {inout} \
+   CONFIG.PSU_MIO_19_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_DIRECTION {in} \
+   CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_1_POLARITY {Default} \
+   CONFIG.PSU_MIO_1_SLEW {fast} \
+   CONFIG.PSU_MIO_20_DIRECTION {inout} \
+   CONFIG.PSU_MIO_20_POLARITY {Default} \
+   CONFIG.PSU_MIO_21_DIRECTION {inout} \
+   CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_21_POLARITY {Default} \
+   CONFIG.PSU_MIO_22_DIRECTION {out} \
+   CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \
+   CONFIG.PSU_MIO_22_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_22_POLARITY {Default} \
+   CONFIG.PSU_MIO_23_DIRECTION {inout} \
+   CONFIG.PSU_MIO_23_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_DIRECTION {in} \
+   CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_24_POLARITY {Default} \
+   CONFIG.PSU_MIO_24_SLEW {fast} \
+   CONFIG.PSU_MIO_25_DIRECTION {inout} \
+   CONFIG.PSU_MIO_25_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_DIRECTION {in} \
+   CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_26_POLARITY {Default} \
+   CONFIG.PSU_MIO_26_SLEW {fast} \
+   CONFIG.PSU_MIO_27_DIRECTION {out} \
+   CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_27_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_DIRECTION {in} \
+   CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_28_POLARITY {Default} \
+   CONFIG.PSU_MIO_28_SLEW {fast} \
+   CONFIG.PSU_MIO_29_DIRECTION {out} \
+   CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_29_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_DIRECTION {in} \
+   CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_2_POLARITY {Default} \
+   CONFIG.PSU_MIO_2_SLEW {fast} \
+   CONFIG.PSU_MIO_30_DIRECTION {in} \
+   CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_30_POLARITY {Default} \
+   CONFIG.PSU_MIO_30_SLEW {fast} \
+   CONFIG.PSU_MIO_31_DIRECTION {inout} \
+   CONFIG.PSU_MIO_31_POLARITY {Default} \
+   CONFIG.PSU_MIO_32_DIRECTION {out} \
+   CONFIG.PSU_MIO_32_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_32_POLARITY {Default} \
+   CONFIG.PSU_MIO_33_DIRECTION {out} \
+   CONFIG.PSU_MIO_33_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_33_POLARITY {Default} \
+   CONFIG.PSU_MIO_34_DIRECTION {out} \
+   CONFIG.PSU_MIO_34_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_34_POLARITY {Default} \
+   CONFIG.PSU_MIO_35_DIRECTION {inout} \
+   CONFIG.PSU_MIO_35_POLARITY {Default} \
+   CONFIG.PSU_MIO_36_DIRECTION {inout} \
+   CONFIG.PSU_MIO_36_POLARITY {Default} \
+   CONFIG.PSU_MIO_37_DIRECTION {inout} \
+   CONFIG.PSU_MIO_37_POLARITY {Default} \
+   CONFIG.PSU_MIO_38_DIRECTION {inout} \
+   CONFIG.PSU_MIO_38_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_DIRECTION {inout} \
+   CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_39_POLARITY {Default} \
+   CONFIG.PSU_MIO_39_SLEW {fast} \
+   CONFIG.PSU_MIO_3_DIRECTION {out} \
+   CONFIG.PSU_MIO_3_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_3_POLARITY {Default} \
+   CONFIG.PSU_MIO_40_DIRECTION {inout} \
+   CONFIG.PSU_MIO_40_POLARITY {Default} \
+   CONFIG.PSU_MIO_41_DIRECTION {inout} \
+   CONFIG.PSU_MIO_41_POLARITY {Default} \
+   CONFIG.PSU_MIO_42_DIRECTION {inout} \
+   CONFIG.PSU_MIO_42_POLARITY {Default} \
+   CONFIG.PSU_MIO_43_DIRECTION {inout} \
+   CONFIG.PSU_MIO_43_POLARITY {Default} \
+   CONFIG.PSU_MIO_44_DIRECTION {inout} \
+   CONFIG.PSU_MIO_44_POLARITY {Default} \
+   CONFIG.PSU_MIO_45_DIRECTION {inout} \
+   CONFIG.PSU_MIO_45_POLARITY {Default} \
+   CONFIG.PSU_MIO_46_DIRECTION {inout} \
+   CONFIG.PSU_MIO_46_POLARITY {Default} \
+   CONFIG.PSU_MIO_47_DIRECTION {inout} \
+   CONFIG.PSU_MIO_47_POLARITY {Default} \
+   CONFIG.PSU_MIO_48_DIRECTION {inout} \
+   CONFIG.PSU_MIO_48_POLARITY {Default} \
+   CONFIG.PSU_MIO_49_DIRECTION {inout} \
+   CONFIG.PSU_MIO_49_POLARITY {Default} \
+   CONFIG.PSU_MIO_4_DIRECTION {inout} \
+   CONFIG.PSU_MIO_4_POLARITY {Default} \
+   CONFIG.PSU_MIO_50_DIRECTION {inout} \
+   CONFIG.PSU_MIO_50_POLARITY {Default} \
+   CONFIG.PSU_MIO_51_DIRECTION {out} \
+   CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_51_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_DIRECTION {in} \
+   CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_52_POLARITY {Default} \
+   CONFIG.PSU_MIO_52_SLEW {fast} \
+   CONFIG.PSU_MIO_53_DIRECTION {in} \
+   CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_53_POLARITY {Default} \
+   CONFIG.PSU_MIO_53_SLEW {fast} \
+   CONFIG.PSU_MIO_54_DIRECTION {inout} \
+   CONFIG.PSU_MIO_54_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_DIRECTION {in} \
+   CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_55_POLARITY {Default} \
+   CONFIG.PSU_MIO_55_SLEW {fast} \
+   CONFIG.PSU_MIO_56_DIRECTION {inout} \
+   CONFIG.PSU_MIO_56_POLARITY {Default} \
+   CONFIG.PSU_MIO_57_DIRECTION {inout} \
+   CONFIG.PSU_MIO_57_POLARITY {Default} \
+   CONFIG.PSU_MIO_58_DIRECTION {out} \
+   CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_58_POLARITY {Default} \
+   CONFIG.PSU_MIO_59_DIRECTION {inout} \
+   CONFIG.PSU_MIO_59_POLARITY {Default} \
+   CONFIG.PSU_MIO_5_DIRECTION {inout} \
+   CONFIG.PSU_MIO_5_POLARITY {Default} \
+   CONFIG.PSU_MIO_60_DIRECTION {inout} \
+   CONFIG.PSU_MIO_60_POLARITY {Default} \
+   CONFIG.PSU_MIO_61_DIRECTION {inout} \
+   CONFIG.PSU_MIO_61_POLARITY {Default} \
+   CONFIG.PSU_MIO_62_DIRECTION {inout} \
+   CONFIG.PSU_MIO_62_POLARITY {Default} \
+   CONFIG.PSU_MIO_63_DIRECTION {inout} \
+   CONFIG.PSU_MIO_63_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_DIRECTION {in} \
+   CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_64_POLARITY {Default} \
+   CONFIG.PSU_MIO_64_SLEW {fast} \
+   CONFIG.PSU_MIO_65_DIRECTION {in} \
+   CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_65_POLARITY {Default} \
+   CONFIG.PSU_MIO_65_SLEW {fast} \
+   CONFIG.PSU_MIO_66_DIRECTION {inout} \
+   CONFIG.PSU_MIO_66_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_DIRECTION {in} \
+   CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \
+   CONFIG.PSU_MIO_67_POLARITY {Default} \
+   CONFIG.PSU_MIO_67_SLEW {fast} \
+   CONFIG.PSU_MIO_68_DIRECTION {inout} \
+   CONFIG.PSU_MIO_68_POLARITY {Default} \
+   CONFIG.PSU_MIO_69_DIRECTION {inout} \
+   CONFIG.PSU_MIO_69_POLARITY {Default} \
+   CONFIG.PSU_MIO_6_DIRECTION {inout} \
+   CONFIG.PSU_MIO_6_POLARITY {Default} \
+   CONFIG.PSU_MIO_70_DIRECTION {out} \
+   CONFIG.PSU_MIO_70_INPUT_TYPE {cmos} \
+   CONFIG.PSU_MIO_70_POLARITY {Default} \
+   CONFIG.PSU_MIO_71_DIRECTION {inout} \
+   CONFIG.PSU_MIO_71_POLARITY {Default} \
+   CONFIG.PSU_MIO_72_DIRECTION {inout} \
+   CONFIG.PSU_MIO_72_POLARITY {Default} \
+   CONFIG.PSU_MIO_73_DIRECTION {inout} \
+   CONFIG.PSU_MIO_73_POLARITY {Default} \
+   CONFIG.PSU_MIO_74_DIRECTION {inout} \
+   CONFIG.PSU_MIO_74_POLARITY {Default} \
+   CONFIG.PSU_MIO_75_DIRECTION {inout} \
+   CONFIG.PSU_MIO_75_POLARITY {Default} \
+   CONFIG.PSU_MIO_76_DIRECTION {inout} \
+   CONFIG.PSU_MIO_76_POLARITY {Default} \
+   CONFIG.PSU_MIO_77_DIRECTION {inout} \
+   CONFIG.PSU_MIO_77_POLARITY {Default} \
+   CONFIG.PSU_MIO_7_DIRECTION {inout} \
+   CONFIG.PSU_MIO_7_POLARITY {Default} \
+   CONFIG.PSU_MIO_8_DIRECTION {inout} \
+   CONFIG.PSU_MIO_8_POLARITY {Default} \
+   CONFIG.PSU_MIO_9_DIRECTION {inout} \
+   CONFIG.PSU_MIO_9_POLARITY {Default} \
+   CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \
+   CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \
+   CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+   CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+   CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \
+   CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+   CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666656} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \
+   CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576040} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214443} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029572} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+   CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+   CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333313} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+   CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \
+   CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724136} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {500} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {400} \
+   CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+   CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {24.999975} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {4} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {299.999700} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {374.999625} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
+   CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \
+   CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+   CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \
+   CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+   CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+   CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+   CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+   CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+   CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \
+   CONFIG.PSU__DDRC__ADDR_MIRROR {1} \
+   CONFIG.PSU__DDRC__AL {0} \
+   CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \
+   CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \
+   CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+   CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \
+   CONFIG.PSU__DDRC__CL {NA} \
+   CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+   CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+   CONFIG.PSU__DDRC__COMPONENTS {Components} \
+   CONFIG.PSU__DDRC__CWL {NA} \
+   CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \
+   CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \
+   CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \
+   CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \
+   CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+   CONFIG.PSU__DDRC__DEVICE_CAPACITY {16384 MBits} \
+   CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+   CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+   CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+   CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+   CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+   CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+   CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+   CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+   CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+   CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+   CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+   CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+   CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+   CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+   CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+   CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+   CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+   CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+   CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+   CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+   CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \
+   CONFIG.PSU__DDRC__ECC {Disabled} \
+   CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
+   CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {1} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+   CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+   CONFIG.PSU__DDRC__FGRM {NA} \
+   CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+   CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {Normal (0-85)} \
+   CONFIG.PSU__DDRC__LP_ASR {NA} \
+   CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \
+   CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \
+   CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+   CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+   CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
+   CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} \
+   CONFIG.PSU__DDRC__SB_TARGET {NA} \
+   CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \
+   CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \
+   CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+   CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+   CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+   CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+   CONFIG.PSU__DDRC__T_FAW {40.0} \
+   CONFIG.PSU__DDRC__T_RAS_MIN {42} \
+   CONFIG.PSU__DDRC__T_RC {63} \
+   CONFIG.PSU__DDRC__T_RCD {10} \
+   CONFIG.PSU__DDRC__T_RP {12} \
+   CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+   CONFIG.PSU__DDRC__VREF {0} \
+   CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+   CONFIG.PSU__DDR_QOS_ENABLE {1} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP0_RDQOS {7} \
+   CONFIG.PSU__DDR_QOS_HP0_WRQOS {15} \
+   CONFIG.PSU__DDR_QOS_HP1_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP1_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP2_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_RDQOS {3} \
+   CONFIG.PSU__DDR_QOS_HP3_WRQOS {3} \
+   CONFIG.PSU__DDR_QOS_PORT0_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT1_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN1_TYPE {Low Latency} \
+   CONFIG.PSU__DDR_QOS_PORT2_VN2_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT3_TYPE {Video Traffic} \
+   CONFIG.PSU__DDR_QOS_PORT4_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_PORT5_TYPE {Best Effort} \
+   CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {0} \
+   CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {16} \
+   CONFIG.PSU__DDR_QOS_WR_THRSHLD {16} \
+   CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+   CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+   CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DLL__ISUSED {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+   CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+   CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+   CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \
+   CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+   CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \
+   CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+   CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+   CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+   CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+   CONFIG.PSU__FPGA_PL1_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL2_ENABLE {0} \
+   CONFIG.PSU__FPGA_PL3_ENABLE {0} \
+   CONFIG.PSU__GEM3_COHERENCY {0} \
+   CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__GEM__TSU__ENABLE {0} \
+   CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \
+   CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \
+   CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \
+   CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__GT__LINK_SPEED {HBR} \
+   CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+   CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+   CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+   CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 4 .. 5} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+   CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+   CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100.000000} \
+   CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100.000000} \
+   CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+   CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__OVERRIDE__BASIC_CLOCK {1} \
+   CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+   CONFIG.PSU__PL_CLK1_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK2_BUF {FALSE} \
+   CONFIG.PSU__PL_CLK3_BUF {FALSE} \
+   CONFIG.PSU__PMU_COHERENCY {0} \
+   CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
+   CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPI0__IO {MIO 26} \
+   CONFIG.PSU__PMU__GPI1__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI2__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPI5__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO0__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO0__IO {MIO 32} \
+   CONFIG.PSU__PMU__GPO1__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO1__IO {MIO 33} \
+   CONFIG.PSU__PMU__GPO2__ENABLE {1} \
+   CONFIG.PSU__PMU__GPO2__IO {MIO 34} \
+   CONFIG.PSU__PMU__GPO2__POLARITY {high} \
+   CONFIG.PSU__PMU__GPO3__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO4__ENABLE {0} \
+   CONFIG.PSU__PMU__GPO5__ENABLE {0} \
+   CONFIG.PSU__PMU__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
+   CONFIG.PSU__PRESET_APPLIED {1} \
+   CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;1|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;1|S_AXI_HP1_FPD:NA;1|S_AXI_HP0_FPD:NA;1|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;1|SATA1:NonSecure;0|SATA0:NonSecure;0|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;0|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;0|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1} \
+   CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;1|LPD;USB3_1;FF9E0000;FF9EFFFF;1|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;1|LPD;SPI0;FF040000;FF04FFFF;1|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;1|FPD;SATA;FD0C0000;FD0CFFFF;0|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;0|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;0|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_GPV;FD700000;FD7FFFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|FPD;CCI_GPV;FD6E0000;FD6EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1} \
+   CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+   CONFIG.PSU__QSPI_COHERENCY {0} \
+   CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {0} \
+   CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+   CONFIG.PSU__SATA__LANE1__ENABLE {0} \
+   CONFIG.PSU__SATA__PERIPHERAL__ENABLE {0} \
+   CONFIG.PSU__SAXIGP2__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP3__DATA_WIDTH {32} \
+   CONFIG.PSU__SAXIGP4__DATA_WIDTH {32} \
+   CONFIG.PSU__SD0_COHERENCY {0} \
+   CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD0__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD0__GRP_CD__ENABLE {1} \
+   CONFIG.PSU__SD0__GRP_CD__IO {MIO 24} \
+   CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD0__PERIPHERAL__IO {MIO 13 .. 16 21 22} \
+   CONFIG.PSU__SD0__RESET__ENABLE {0} \
+   CONFIG.PSU__SD0__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SD1_COHERENCY {0} \
+   CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+   CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+   CONFIG.PSU__SD1__GRP_CD__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+   CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+   CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+   CONFIG.PSU__SD1__RESET__ENABLE {0} \
+   CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+   CONFIG.PSU__SPI0__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI0__GRP_SS0__IO {MIO 41} \
+   CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI0__PERIPHERAL__IO {MIO 38 .. 43} \
+   CONFIG.PSU__SPI1__GRP_SS0__ENABLE {1} \
+   CONFIG.PSU__SPI1__GRP_SS0__IO {MIO 9} \
+   CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
+   CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
+   CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SPI1__PERIPHERAL__IO {MIO 6 .. 11} \
+   CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+   CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+   CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+   CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+   CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+   CONFIG.PSU__UART0__BAUD_RATE {115200} \
+   CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 2 .. 3} \
+   CONFIG.PSU__UART1__BAUD_RATE {115200} \
+   CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+   CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 0 .. 1} \
+   CONFIG.PSU__USB0_COHERENCY {0} \
+   CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+   CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB0__RESET__ENABLE {0} \
+   CONFIG.PSU__USB1_COHERENCY {0} \
+   CONFIG.PSU__USB1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB1__PERIPHERAL__IO {MIO 64 .. 75} \
+   CONFIG.PSU__USB1__REF_CLK_FREQ {26} \
+   CONFIG.PSU__USB1__REF_CLK_SEL {Ref Clk0} \
+   CONFIG.PSU__USB1__RESET__ENABLE {0} \
+   CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+   CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {1} \
+   CONFIG.PSU__USB3_1__PERIPHERAL__IO {GT Lane3} \
+   CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+   CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+   CONFIG.PSU__USE__IRQ0 {0} \
+   CONFIG.PSU__USE__M_AXI_GP0 {1} \
+   CONFIG.PSU__USE__M_AXI_GP1 {0} \
+   CONFIG.PSU__USE__M_AXI_GP2 {0} \
+   CONFIG.PSU__USE__S_AXI_GP2 {1} \
+   CONFIG.PSU__USE__S_AXI_GP3 {1} \
+   CONFIG.PSU__USE__S_AXI_GP4 {1} \
+   CONFIG.SUBPRESET1 {Custom} \
+ ] $zynq_ultra_ps_e_0
+
+  # Create interface connections
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in1_mem [get_bd_intf_pins mmult_0/m_axi_in1_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP0_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_in2_mem [get_bd_intf_pins mmult_0/m_axi_in2_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP1_FPD]
+  connect_bd_intf_net -intf_net mmult_0_m_axi_out_mem [get_bd_intf_pins mmult_0/m_axi_out_mem] [get_bd_intf_pins zynq_ultra_ps_e_0/S_AXI_HP2_FPD]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M00_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins ps8_0_axi_periph/M00_AXI]
+  connect_bd_intf_net -intf_net ps8_0_axi_periph_M01_AXI [get_bd_intf_pins mmult_0/s_axi_params] [get_bd_intf_pins ps8_0_axi_periph/M01_AXI]
+  connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_FPD [get_bd_intf_pins ps8_0_axi_periph/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_FPD]
+
+  # Create port connections
+  connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_ps8_0_100M/dcm_locked]
+  connect_bd_net -net rst_ps8_0_100M_peripheral_aresetn [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins mmult_0/ap_rst_n] [get_bd_pins ps8_0_axi_periph/ARESETN] [get_bd_pins ps8_0_axi_periph/M00_ARESETN] [get_bd_pins ps8_0_axi_periph/M01_ARESETN] [get_bd_pins ps8_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps8_0_100M/peripheral_aresetn]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out_300] [get_bd_pins mmult_0/ap_clk] [get_bd_pins ps8_0_axi_periph/ACLK] [get_bd_pins ps8_0_axi_periph/M00_ACLK] [get_bd_pins ps8_0_axi_periph/M01_ACLK] [get_bd_pins ps8_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps8_0_100M/slowest_sync_clk] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp0_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp1_fpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/saxihp2_fpd_aclk]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk1 [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins clk_wiz_0/resetn] [get_bd_pins rst_ps8_0_100M/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+
+  # Create address segments
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_DDR_LOW] -force
+  assign_bd_address -offset 0x00000000 -range 0x80000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_DDR_LOW] -force
+  assign_bd_address -offset 0xA0000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] -force
+  assign_bd_address -offset 0xA0010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs mmult_0/s_axi_params/Reg] -force
+
+  # Exclude Address Segments
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in1_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP2/HP0_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_in2_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP3/HP1_LPS_OCM]
+  exclude_bd_addr_seg -offset 0xFF000000 -range 0x01000000 -target_address_space [get_bd_addr_spaces mmult_0/Data_m_axi_out_mem] [get_bd_addr_segs zynq_ultra_ps_e_0/SAXIGP4/HP2_LPS_OCM]
+
+
+  # Restore current instance
+  current_bd_instance $oldCurInst
+
+  validate_bd_design
+  save_bd_design
+}
+# End of create_root_design()
+
+
+##################################################################
+# MAIN FLOW
+##################################################################
+
+create_root_design ""
+
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/constraints/mmult_ooc.xdc

@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/doc/ReleaseNotes.txt

@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.mdd

@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v1_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 1.0;
+
+END driver
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/data/mmult.tcl

@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/Makefile

@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.c

@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult.h

@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_hw.h

@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_linux.c

@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/drivers/mmult_v1_0/src/xmmult_sinit.c

@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/verilog/mmult_params_s_axi.v

@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/hdl/vhdl/mmult_params_s_axi.vhd

@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;

hls/lab2/exported_ips/xilinx_com_hls_exercise_2/xgui/mmult_v1_0.tcl

@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/constraints/mmult_ooc.xdc

@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/doc/ReleaseNotes.txt

@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.mdd

@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v2_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 2.0;
+
+END driver
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/data/mmult.tcl

@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/Makefile

@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.c

@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult.h

@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_hw.h

@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_linux.c

@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/drivers/mmult_v2_0/src/xmmult_sinit.c

@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_params_s_axi.v

@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/verilog/mmult_urem_96ns_3bkb.v

@@ -0,0 +1,164 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+
+module mmult_urem_96ns_3bkb_div_u
+#(parameter
+    in0_WIDTH = 32,
+    in1_WIDTH = 32,
+    out_WIDTH = 32
+)
+(
+    input                       clk,
+    input                       reset,
+    input                       ce,
+    input       [in0_WIDTH-1:0] dividend,
+    input       [in1_WIDTH-1:0] divisor,
+    output wire [out_WIDTH-1:0] quot,
+    output wire [out_WIDTH-1:0] remd
+);
+
+localparam cal_WIDTH = (in0_WIDTH > in1_WIDTH)? in0_WIDTH : in1_WIDTH;
+
+//------------------------Local signal-------------------
+reg  [in0_WIDTH-1:0] dividend_tmp[0:in0_WIDTH];
+reg  [in1_WIDTH-1:0] divisor_tmp[0:in0_WIDTH];
+reg  [in0_WIDTH-1:0] remd_tmp[0:in0_WIDTH];
+wire [in0_WIDTH-1:0] comb_tmp[0:in0_WIDTH-1];
+wire [cal_WIDTH:0]   cal_tmp[0:in0_WIDTH-1];
+//------------------------Body---------------------------
+assign  quot    = dividend_tmp[in0_WIDTH];
+assign  remd    = remd_tmp[in0_WIDTH];
+
+// dividend_tmp[0], divisor_tmp[0], remd_tmp[0]
+always @(posedge clk)
+begin
+    if (ce) begin
+        dividend_tmp[0] <= dividend;
+        divisor_tmp[0]  <= divisor;
+        remd_tmp[0]     <= 1'b0;
+    end
+end
+
+genvar i;
+generate 
+    for (i = 0; i < in0_WIDTH; i = i + 1)
+    begin : loop
+        if (in0_WIDTH == 1) assign  comb_tmp[i]     = dividend_tmp[i][0];
+        else                assign  comb_tmp[i]     = {remd_tmp[i][in0_WIDTH-2:0], dividend_tmp[i][in0_WIDTH-1]};
+        assign  cal_tmp[i]      = {1'b0, comb_tmp[i]} - {1'b0, divisor_tmp[i]};
+
+        always @(posedge clk)
+        begin
+            if (ce) begin
+                if (in0_WIDTH == 1) dividend_tmp[i+1] <= ~cal_tmp[i][cal_WIDTH];
+                else                dividend_tmp[i+1] <= {dividend_tmp[i][in0_WIDTH-2:0], ~cal_tmp[i][cal_WIDTH]};
+                divisor_tmp[i+1]  <= divisor_tmp[i];
+                remd_tmp[i+1]     <= cal_tmp[i][cal_WIDTH]? comb_tmp[i] : cal_tmp[i][in0_WIDTH-1:0];
+            end
+        end
+    end
+endgenerate
+
+endmodule
+
+module mmult_urem_96ns_3bkb_div
+#(parameter
+        in0_WIDTH   = 32,
+        in1_WIDTH   = 32,
+        out_WIDTH   = 32
+)
+(
+        input                           clk,
+        input                           reset,
+        input                           ce,
+        input           [in0_WIDTH-1:0] dividend,
+        input           [in1_WIDTH-1:0] divisor,
+        output  reg     [out_WIDTH-1:0] quot,
+        output  reg     [out_WIDTH-1:0] remd
+);
+//------------------------Local signal-------------------
+reg     [in0_WIDTH-1:0] dividend0;
+reg     [in1_WIDTH-1:0] divisor0;
+wire    [in0_WIDTH-1:0] dividend_u;
+wire    [in1_WIDTH-1:0] divisor_u;
+wire    [out_WIDTH-1:0] quot_u;
+wire    [out_WIDTH-1:0] remd_u;
+//------------------------Instantiation------------------
+mmult_urem_96ns_3bkb_div_u #(
+    .in0_WIDTH      ( in0_WIDTH ),
+    .in1_WIDTH      ( in1_WIDTH ),
+    .out_WIDTH      ( out_WIDTH )
+) mmult_urem_96ns_3bkb_div_u_0 (
+    .clk      ( clk ),
+    .reset    ( reset ),
+    .ce       ( ce ),
+    .dividend ( dividend_u ),
+    .divisor  ( divisor_u ),
+    .quot     ( quot_u ),
+    .remd     ( remd_u )
+);
+//------------------------Body---------------------------
+assign dividend_u = dividend0;
+assign divisor_u = divisor0;
+
+always @(posedge clk)
+begin
+    if (ce) begin
+        dividend0 <= dividend;
+        divisor0  <= divisor;
+    end
+end
+
+always @(posedge clk)
+begin
+    if (ce) begin
+        quot <= quot_u;
+        remd <= remd_u;
+    end
+end
+
+endmodule
+
+
+`timescale 1 ns / 1 ps
+module mmult_urem_96ns_3bkb(
+    clk,
+    reset,
+    ce,
+    din0,
+    din1,
+    dout);
+
+parameter ID = 32'd1;
+parameter NUM_STAGE = 32'd1;
+parameter din0_WIDTH = 32'd1;
+parameter din1_WIDTH = 32'd1;
+parameter dout_WIDTH = 32'd1;
+input clk;
+input reset;
+input ce;
+input[din0_WIDTH - 1:0] din0;
+input[din1_WIDTH - 1:0] din1;
+output[dout_WIDTH - 1:0] dout;
+
+wire[dout_WIDTH - 1:0] sig_quot;
+
+
+mmult_urem_96ns_3bkb_div #(
+.in0_WIDTH( din0_WIDTH ),
+.in1_WIDTH( din1_WIDTH ),
+.out_WIDTH( dout_WIDTH ))
+mmult_urem_96ns_3bkb_div_U(
+    .dividend( din0 ),
+    .divisor( din1 ),
+    .remd( dout ),
+    .quot( sig_quot ),
+    .clk( clk ),
+    .ce( ce ),
+    .reset( reset ));
+
+endmodule
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_params_s_axi.vhd

@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/hdl/vhdl/mmult_urem_96ns_3bkb.vhd

@@ -0,0 +1,219 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mmult_urem_96ns_3bkb_div_u is
+    generic (
+        in0_WIDTH   : INTEGER :=32;
+        in1_WIDTH   : INTEGER :=32;
+        out_WIDTH   : INTEGER :=32);
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        ce          : in  STD_LOGIC;
+        dividend    : in  STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+        divisor     : in  STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+        quot        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+        remd        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
+
+    function max (left, right : INTEGER) return INTEGER is
+    begin
+        if left > right then return left;
+        else return right;
+        end if;
+    end max;
+
+end entity;
+
+architecture rtl of mmult_urem_96ns_3bkb_div_u is
+    constant cal_WIDTH      : INTEGER := max(in0_WIDTH, in1_WIDTH);
+    type  in0_vector  is array(INTEGER range <>) of UNSIGNED(in0_WIDTH-1 downto 0);
+    type  in1_vector  is array(INTEGER range <>) of UNSIGNED(in1_WIDTH-1 downto 0);
+    type  cal_vector  is array(INTEGER range <>) of UNSIGNED(cal_WIDTH downto 0);
+
+    signal dividend_tmp     : in0_vector(0 to in0_WIDTH);
+    signal divisor_tmp      : in1_vector(0 to in0_WIDTH);
+    signal remd_tmp         : in0_vector(0 to in0_WIDTH);
+    signal comb_tmp         : in0_vector(0 to in0_WIDTH-1);
+    signal cal_tmp          : cal_vector(0 to in0_WIDTH-1);
+begin
+    quot   <= STD_LOGIC_VECTOR(RESIZE(dividend_tmp(in0_WIDTH), out_WIDTH));
+    remd   <= STD_LOGIC_VECTOR(RESIZE(remd_tmp(in0_WIDTH), out_WIDTH));
+
+    tran_tmp_proc : process (clk)
+    begin
+        if (clk'event and clk='1') then
+            if (ce = '1') then
+                dividend_tmp(0) <= UNSIGNED(dividend);
+                divisor_tmp(0)  <= UNSIGNED(divisor);
+                remd_tmp(0) <= (others => '0');
+            end if;
+        end if;
+    end process tran_tmp_proc;
+
+    run_proc: for i in 0 to in0_WIDTH-1 generate
+    begin
+        comb_tmp(i) <= remd_tmp(i)(in0_WIDTH-2 downto 0) & dividend_tmp(i)(in0_WIDTH-1);
+        cal_tmp(i)  <= ('0' & comb_tmp(i)) - ('0' & divisor_tmp(i));
+
+        process (clk)
+        begin
+            if (clk'event and clk='1') then
+                if (ce = '1') then
+                    dividend_tmp(i+1) <= dividend_tmp(i)(in0_WIDTH-2 downto 0) & (not cal_tmp(i)(cal_WIDTH));
+                    divisor_tmp(i+1)  <= divisor_tmp(i);
+                    if cal_tmp(i)(cal_WIDTH) = '1' then
+                        remd_tmp(i+1) <= comb_tmp(i);
+                    else
+                        remd_tmp(i+1) <= cal_tmp(i)(in0_WIDTH-1 downto 0);
+                    end if;
+                end if;
+            end if;
+        end process;
+    end generate run_proc;
+
+end architecture;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mmult_urem_96ns_3bkb_div is
+    generic (
+        in0_WIDTH   : INTEGER :=32;
+        in1_WIDTH   : INTEGER :=32;
+        out_WIDTH   : INTEGER :=32);
+    port (
+        clk         : in  STD_LOGIC;
+        reset       : in  STD_LOGIC;
+        ce          : in  STD_LOGIC;
+        dividend    : in  STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+        divisor     : in  STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+        quot        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+        remd        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
+end entity;
+
+architecture rtl of mmult_urem_96ns_3bkb_div is
+    component mmult_urem_96ns_3bkb_div_u is
+        generic (
+            in0_WIDTH   : INTEGER :=32;
+            in1_WIDTH   : INTEGER :=32;
+            out_WIDTH   : INTEGER :=32);
+        port (
+            reset       : in  STD_LOGIC;
+            clk         : in  STD_LOGIC;
+            ce          : in  STD_LOGIC;
+            dividend    : in  STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+            divisor     : in  STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+            quot        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+            remd        : out STD_LOGIC_VECTOR(out_WIDTH-1 downto 0));
+    end component;
+
+    signal dividend0  : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+    signal divisor0   : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+    signal dividend_u : STD_LOGIC_VECTOR(in0_WIDTH-1 downto 0);
+    signal divisor_u  : STD_LOGIC_VECTOR(in1_WIDTH-1 downto 0);
+    signal quot_u     : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+    signal remd_u     : STD_LOGIC_VECTOR(out_WIDTH-1 downto 0);
+begin
+    mmult_urem_96ns_3bkb_div_u_0 : mmult_urem_96ns_3bkb_div_u
+        generic map(
+            in0_WIDTH   => in0_WIDTH,
+            in1_WIDTH   => in1_WIDTH,
+            out_WIDTH   => out_WIDTH)
+        port map(
+            clk         => clk,
+            reset       => reset,
+            ce          => ce,
+            dividend    => dividend_u,
+            divisor     => divisor_u,
+            quot        => quot_u,
+            remd        => remd_u);
+
+    dividend_u  <= dividend0;
+    divisor_u   <= divisor0;
+
+process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            dividend0 <= dividend;
+            divisor0 <= divisor;
+        end if;
+    end if;
+end process;
+
+process (clk)
+begin
+    if (clk'event and clk = '1') then
+        if (ce = '1') then
+            quot <= quot_u;
+            remd <= remd_u;
+        end if;
+    end if;
+end process;
+
+end architecture;
+
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_urem_96ns_3bkb is
+    generic (
+        ID : INTEGER;
+        NUM_STAGE : INTEGER;
+        din0_WIDTH : INTEGER;
+        din1_WIDTH : INTEGER;
+        dout_WIDTH : INTEGER);
+    port (
+        clk : IN STD_LOGIC;
+        reset : IN STD_LOGIC;
+        ce : IN STD_LOGIC;
+        din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
+        din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
+        dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_urem_96ns_3bkb is
+    component mmult_urem_96ns_3bkb_div is
+        generic (
+            in0_WIDTH : INTEGER;
+            in1_WIDTH : INTEGER;
+            out_WIDTH : INTEGER);
+        port (
+            dividend : IN STD_LOGIC_VECTOR;
+            divisor : IN STD_LOGIC_VECTOR;
+            remd : OUT STD_LOGIC_VECTOR;
+            quot : OUT STD_LOGIC_VECTOR;
+            clk : IN STD_LOGIC;
+            ce : IN STD_LOGIC;
+            reset : IN STD_LOGIC);
+    end component;
+
+    signal sig_quot : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
+    signal sig_remd : STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0);
+
+
+begin
+    mmult_urem_96ns_3bkb_div_U :  component mmult_urem_96ns_3bkb_div
+    generic map (
+        in0_WIDTH => din0_WIDTH,
+        in1_WIDTH => din1_WIDTH,
+        out_WIDTH => dout_WIDTH)
+    port map (
+        dividend => din0,
+        divisor => din1,
+        remd => dout,
+        quot => sig_quot,
+        clk => clk,
+        ce => ce,
+        reset => reset);
+
+end architecture;
+
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_3/xgui/mmult_v2_0.tcl

@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/constraints/mmult_ooc.xdc

@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/doc/ReleaseNotes.txt

@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.mdd

@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v3_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 3.0;
+
+END driver
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/data/mmult.tcl

@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/Makefile

@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.c

@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult.h

@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_hw.h

@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_linux.c

@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/drivers/mmult_v3_0/src/xmmult_sinit.c

@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_in1_loc.v

@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_in1_loc_ram mmult_in1_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/verilog/mmult_params_s_axi.v

@@ -0,0 +1,393 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1ns/1ps
+module mmult_params_s_axi
+#(parameter
+    C_S_AXI_ADDR_WIDTH = 6,
+    C_S_AXI_DATA_WIDTH = 32
+)(
+    input  wire                          ACLK,
+    input  wire                          ARESET,
+    input  wire                          ACLK_EN,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
+    input  wire                          AWVALID,
+    output wire                          AWREADY,
+    input  wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
+    input  wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
+    input  wire                          WVALID,
+    output wire                          WREADY,
+    output wire [1:0]                    BRESP,
+    output wire                          BVALID,
+    input  wire                          BREADY,
+    input  wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
+    input  wire                          ARVALID,
+    output wire                          ARREADY,
+    output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
+    output wire [1:0]                    RRESP,
+    output wire                          RVALID,
+    input  wire                          RREADY,
+    output wire                          interrupt,
+    output wire                          ap_start,
+    input  wire                          ap_done,
+    input  wire                          ap_ready,
+    input  wire                          ap_idle,
+    output wire [31:0]                   in1,
+    output wire [31:0]                   in2,
+    output wire [31:0]                   out_r,
+    output wire [31:0]                   dim
+);
+//------------------------Address Info-------------------
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+//------------------------Parameter----------------------
+localparam
+    ADDR_AP_CTRL      = 6'h00,
+    ADDR_GIE          = 6'h04,
+    ADDR_IER          = 6'h08,
+    ADDR_ISR          = 6'h0c,
+    ADDR_IN1_DATA_0   = 6'h10,
+    ADDR_IN1_CTRL     = 6'h14,
+    ADDR_IN2_DATA_0   = 6'h18,
+    ADDR_IN2_CTRL     = 6'h1c,
+    ADDR_OUT_R_DATA_0 = 6'h20,
+    ADDR_OUT_R_CTRL   = 6'h24,
+    ADDR_DIM_DATA_0   = 6'h28,
+    ADDR_DIM_CTRL     = 6'h2c,
+    WRIDLE            = 2'd0,
+    WRDATA            = 2'd1,
+    WRRESP            = 2'd2,
+    WRRESET           = 2'd3,
+    RDIDLE            = 2'd0,
+    RDDATA            = 2'd1,
+    RDRESET           = 2'd2,
+    ADDR_BITS         = 6;
+
+//------------------------Local signal-------------------
+    reg  [1:0]                    wstate = WRRESET;
+    reg  [1:0]                    wnext;
+    reg  [ADDR_BITS-1:0]          waddr;
+    wire [31:0]                   wmask;
+    wire                          aw_hs;
+    wire                          w_hs;
+    reg  [1:0]                    rstate = RDRESET;
+    reg  [1:0]                    rnext;
+    reg  [31:0]                   rdata;
+    wire                          ar_hs;
+    wire [ADDR_BITS-1:0]          raddr;
+    // internal registers
+    reg                           int_ap_idle;
+    reg                           int_ap_ready;
+    reg                           int_ap_done = 1'b0;
+    reg                           int_ap_start = 1'b0;
+    reg                           int_auto_restart = 1'b0;
+    reg                           int_gie = 1'b0;
+    reg  [1:0]                    int_ier = 2'b0;
+    reg  [1:0]                    int_isr = 2'b0;
+    reg  [31:0]                   int_in1 = 'b0;
+    reg  [31:0]                   int_in2 = 'b0;
+    reg  [31:0]                   int_out_r = 'b0;
+    reg  [31:0]                   int_dim = 'b0;
+
+//------------------------Instantiation------------------
+
+//------------------------AXI write fsm------------------
+assign AWREADY = (wstate == WRIDLE);
+assign WREADY  = (wstate == WRDATA);
+assign BRESP   = 2'b00;  // OKAY
+assign BVALID  = (wstate == WRRESP);
+assign wmask   = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
+assign aw_hs   = AWVALID & AWREADY;
+assign w_hs    = WVALID & WREADY;
+
+// wstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        wstate <= WRRESET;
+    else if (ACLK_EN)
+        wstate <= wnext;
+end
+
+// wnext
+always @(*) begin
+    case (wstate)
+        WRIDLE:
+            if (AWVALID)
+                wnext = WRDATA;
+            else
+                wnext = WRIDLE;
+        WRDATA:
+            if (WVALID)
+                wnext = WRRESP;
+            else
+                wnext = WRDATA;
+        WRRESP:
+            if (BREADY)
+                wnext = WRIDLE;
+            else
+                wnext = WRRESP;
+        default:
+            wnext = WRIDLE;
+    endcase
+end
+
+// waddr
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (aw_hs)
+            waddr <= AWADDR[ADDR_BITS-1:0];
+    end
+end
+
+//------------------------AXI read fsm-------------------
+assign ARREADY = (rstate == RDIDLE);
+assign RDATA   = rdata;
+assign RRESP   = 2'b00;  // OKAY
+assign RVALID  = (rstate == RDDATA);
+assign ar_hs   = ARVALID & ARREADY;
+assign raddr   = ARADDR[ADDR_BITS-1:0];
+
+// rstate
+always @(posedge ACLK) begin
+    if (ARESET)
+        rstate <= RDRESET;
+    else if (ACLK_EN)
+        rstate <= rnext;
+end
+
+// rnext
+always @(*) begin
+    case (rstate)
+        RDIDLE:
+            if (ARVALID)
+                rnext = RDDATA;
+            else
+                rnext = RDIDLE;
+        RDDATA:
+            if (RREADY & RVALID)
+                rnext = RDIDLE;
+            else
+                rnext = RDDATA;
+        default:
+            rnext = RDIDLE;
+    endcase
+end
+
+// rdata
+always @(posedge ACLK) begin
+    if (ACLK_EN) begin
+        if (ar_hs) begin
+            rdata <= 1'b0;
+            case (raddr)
+                ADDR_AP_CTRL: begin
+                    rdata[0] <= int_ap_start;
+                    rdata[1] <= int_ap_done;
+                    rdata[2] <= int_ap_idle;
+                    rdata[3] <= int_ap_ready;
+                    rdata[7] <= int_auto_restart;
+                end
+                ADDR_GIE: begin
+                    rdata <= int_gie;
+                end
+                ADDR_IER: begin
+                    rdata <= int_ier;
+                end
+                ADDR_ISR: begin
+                    rdata <= int_isr;
+                end
+                ADDR_IN1_DATA_0: begin
+                    rdata <= int_in1[31:0];
+                end
+                ADDR_IN2_DATA_0: begin
+                    rdata <= int_in2[31:0];
+                end
+                ADDR_OUT_R_DATA_0: begin
+                    rdata <= int_out_r[31:0];
+                end
+                ADDR_DIM_DATA_0: begin
+                    rdata <= int_dim[31:0];
+                end
+            endcase
+        end
+    end
+end
+
+
+//------------------------Register logic-----------------
+assign interrupt = int_gie & (|int_isr);
+assign ap_start  = int_ap_start;
+assign in1       = int_in1;
+assign in2       = int_in2;
+assign out_r     = int_out_r;
+assign dim       = int_dim;
+// int_ap_start
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_start <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0])
+            int_ap_start <= 1'b1;
+        else if (ap_ready)
+            int_ap_start <= int_auto_restart; // clear on handshake/auto restart
+    end
+end
+
+// int_ap_done
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_done <= 1'b0;
+    else if (ACLK_EN) begin
+        if (ap_done)
+            int_ap_done <= 1'b1;
+        else if (ar_hs && raddr == ADDR_AP_CTRL)
+            int_ap_done <= 1'b0; // clear on read
+    end
+end
+
+// int_ap_idle
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_idle <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_idle <= ap_idle;
+    end
+end
+
+// int_ap_ready
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ap_ready <= 1'b0;
+    else if (ACLK_EN) begin
+            int_ap_ready <= ap_ready;
+    end
+end
+
+// int_auto_restart
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_auto_restart <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_AP_CTRL && WSTRB[0])
+            int_auto_restart <=  WDATA[7];
+    end
+end
+
+// int_gie
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_gie <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_GIE && WSTRB[0])
+            int_gie <= WDATA[0];
+    end
+end
+
+// int_ier
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_ier <= 1'b0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IER && WSTRB[0])
+            int_ier <= WDATA[1:0];
+    end
+end
+
+// int_isr[0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[0] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[0] & ap_done)
+            int_isr[0] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
+    end
+end
+
+// int_isr[1]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_isr[1] <= 1'b0;
+    else if (ACLK_EN) begin
+        if (int_ier[1] & ap_ready)
+            int_isr[1] <= 1'b1;
+        else if (w_hs && waddr == ADDR_ISR && WSTRB[0])
+            int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
+    end
+end
+
+// int_in1[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in1[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN1_DATA_0)
+            int_in1[31:0] <= (WDATA[31:0] & wmask) | (int_in1[31:0] & ~wmask);
+    end
+end
+
+// int_in2[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_in2[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_IN2_DATA_0)
+            int_in2[31:0] <= (WDATA[31:0] & wmask) | (int_in2[31:0] & ~wmask);
+    end
+end
+
+// int_out_r[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_out_r[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_OUT_R_DATA_0)
+            int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
+    end
+end
+
+// int_dim[31:0]
+always @(posedge ACLK) begin
+    if (ARESET)
+        int_dim[31:0] <= 0;
+    else if (ACLK_EN) begin
+        if (w_hs && waddr == ADDR_DIM_DATA_0)
+            int_dim[31:0] <= (WDATA[31:0] & wmask) | (int_dim[31:0] & ~wmask);
+    end
+end
+
+
+//------------------------Memory logic-------------------
+
+endmodule

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_in1_loc.vhd

@@ -0,0 +1,112 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+--
+library ieee; 
+use ieee.std_logic_1164.all; 
+use ieee.std_logic_unsigned.all;
+
+entity mmult_in1_loc_ram is 
+    generic(
+            MEM_TYPE    : string := "block"; 
+            DWIDTH     : integer := 32; 
+            AWIDTH     : integer := 12; 
+            MEM_SIZE    : integer := 4096
+    ); 
+    port (
+          addr0     : in std_logic_vector(AWIDTH-1 downto 0); 
+          ce0       : in std_logic; 
+          d0        : in std_logic_vector(DWIDTH-1 downto 0); 
+          we0       : in std_logic; 
+          q0        : out std_logic_vector(DWIDTH-1 downto 0);
+          clk        : in std_logic 
+    ); 
+end entity; 
+
+
+architecture rtl of mmult_in1_loc_ram is 
+
+signal addr0_tmp : std_logic_vector(AWIDTH-1 downto 0); 
+type mem_array is array (0 to MEM_SIZE-1) of std_logic_vector (DWIDTH-1 downto 0); 
+shared variable ram : mem_array;
+
+attribute syn_ramstyle : string; 
+attribute syn_ramstyle of ram : variable is "block_ram";
+attribute ram_style : string;
+attribute ram_style of ram : variable is MEM_TYPE;
+
+begin 
+
+
+memory_access_guard_0: process (addr0) 
+begin
+      addr0_tmp <= addr0;
+--synthesis translate_off
+      if (CONV_INTEGER(addr0) > mem_size-1) then
+           addr0_tmp <= (others => '0');
+      else 
+           addr0_tmp <= addr0;
+      end if;
+--synthesis translate_on
+end process;
+
+p_memory_access_0: process (clk)  
+begin 
+    if (clk'event and clk = '1') then
+        if (ce0 = '1') then 
+            q0 <= ram(CONV_INTEGER(addr0_tmp));
+            if (we0 = '1') then 
+                ram(CONV_INTEGER(addr0_tmp)) := d0; 
+            end if;
+        end if;
+    end if;
+end process;
+
+
+end rtl;
+
+Library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity mmult_in1_loc is
+    generic (
+        DataWidth : INTEGER := 32;
+        AddressRange : INTEGER := 4096;
+        AddressWidth : INTEGER := 12);
+    port (
+        reset : IN STD_LOGIC;
+        clk : IN STD_LOGIC;
+        address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
+        ce0 : IN STD_LOGIC;
+        we0 : IN STD_LOGIC;
+        d0 : IN STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
+        q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
+end entity;
+
+architecture arch of mmult_in1_loc is
+    component mmult_in1_loc_ram is
+        port (
+            clk : IN STD_LOGIC;
+            addr0 : IN STD_LOGIC_VECTOR;
+            ce0 : IN STD_LOGIC;
+            we0 : IN STD_LOGIC;
+            d0 : IN STD_LOGIC_VECTOR;
+            q0 : OUT STD_LOGIC_VECTOR);
+    end component;
+
+
+
+begin
+    mmult_in1_loc_ram_U :  component mmult_in1_loc_ram
+    port map (
+        clk => clk,
+        addr0 => address0,
+        ce0 => ce0,
+        we0 => we0,
+        d0 => d0,
+        q0 => q0);
+
+end architecture;
+
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/hdl/vhdl/mmult_params_s_axi.vhd

@@ -0,0 +1,439 @@
+-- ==============================================================
+-- Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+-- Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+-- ==============================================================
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.NUMERIC_STD.all;
+
+entity mmult_params_s_axi is
+generic (
+    C_S_AXI_ADDR_WIDTH    : INTEGER := 6;
+    C_S_AXI_DATA_WIDTH    : INTEGER := 32);
+port (
+    ACLK                  :in   STD_LOGIC;
+    ARESET                :in   STD_LOGIC;
+    ACLK_EN               :in   STD_LOGIC;
+    AWADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    AWVALID               :in   STD_LOGIC;
+    AWREADY               :out  STD_LOGIC;
+    WDATA                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    WSTRB                 :in   STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
+    WVALID                :in   STD_LOGIC;
+    WREADY                :out  STD_LOGIC;
+    BRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    BVALID                :out  STD_LOGIC;
+    BREADY                :in   STD_LOGIC;
+    ARADDR                :in   STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
+    ARVALID               :in   STD_LOGIC;
+    ARREADY               :out  STD_LOGIC;
+    RDATA                 :out  STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
+    RRESP                 :out  STD_LOGIC_VECTOR(1 downto 0);
+    RVALID                :out  STD_LOGIC;
+    RREADY                :in   STD_LOGIC;
+    interrupt             :out  STD_LOGIC;
+    ap_start              :out  STD_LOGIC;
+    ap_done               :in   STD_LOGIC;
+    ap_ready              :in   STD_LOGIC;
+    ap_idle               :in   STD_LOGIC;
+    in1                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    in2                   :out  STD_LOGIC_VECTOR(31 downto 0);
+    out_r                 :out  STD_LOGIC_VECTOR(31 downto 0);
+    dim                   :out  STD_LOGIC_VECTOR(31 downto 0)
+);
+end entity mmult_params_s_axi;
+
+-- ------------------------Address Info-------------------
+-- 0x00 : Control signals
+--        bit 0  - ap_start (Read/Write/COH)
+--        bit 1  - ap_done (Read/COR)
+--        bit 2  - ap_idle (Read)
+--        bit 3  - ap_ready (Read)
+--        bit 7  - auto_restart (Read/Write)
+--        others - reserved
+-- 0x04 : Global Interrupt Enable Register
+--        bit 0  - Global Interrupt Enable (Read/Write)
+--        others - reserved
+-- 0x08 : IP Interrupt Enable Register (Read/Write)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x0c : IP Interrupt Status Register (Read/TOW)
+--        bit 0  - Channel 0 (ap_done)
+--        bit 1  - Channel 1 (ap_ready)
+--        others - reserved
+-- 0x10 : Data signal of in1
+--        bit 31~0 - in1[31:0] (Read/Write)
+-- 0x14 : reserved
+-- 0x18 : Data signal of in2
+--        bit 31~0 - in2[31:0] (Read/Write)
+-- 0x1c : reserved
+-- 0x20 : Data signal of out_r
+--        bit 31~0 - out_r[31:0] (Read/Write)
+-- 0x24 : reserved
+-- 0x28 : Data signal of dim
+--        bit 31~0 - dim[31:0] (Read/Write)
+-- 0x2c : reserved
+-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+architecture behave of mmult_params_s_axi is
+    type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset);  -- read and write fsm states
+    signal wstate  : states := wrreset;
+    signal rstate  : states := rdreset;
+    signal wnext, rnext: states;
+    constant ADDR_AP_CTRL      : INTEGER := 16#00#;
+    constant ADDR_GIE          : INTEGER := 16#04#;
+    constant ADDR_IER          : INTEGER := 16#08#;
+    constant ADDR_ISR          : INTEGER := 16#0c#;
+    constant ADDR_IN1_DATA_0   : INTEGER := 16#10#;
+    constant ADDR_IN1_CTRL     : INTEGER := 16#14#;
+    constant ADDR_IN2_DATA_0   : INTEGER := 16#18#;
+    constant ADDR_IN2_CTRL     : INTEGER := 16#1c#;
+    constant ADDR_OUT_R_DATA_0 : INTEGER := 16#20#;
+    constant ADDR_OUT_R_CTRL   : INTEGER := 16#24#;
+    constant ADDR_DIM_DATA_0   : INTEGER := 16#28#;
+    constant ADDR_DIM_CTRL     : INTEGER := 16#2c#;
+    constant ADDR_BITS         : INTEGER := 6;
+
+    signal waddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal wmask               : UNSIGNED(31 downto 0);
+    signal aw_hs               : STD_LOGIC;
+    signal w_hs                : STD_LOGIC;
+    signal rdata_data          : UNSIGNED(31 downto 0);
+    signal ar_hs               : STD_LOGIC;
+    signal raddr               : UNSIGNED(ADDR_BITS-1 downto 0);
+    signal AWREADY_t           : STD_LOGIC;
+    signal WREADY_t            : STD_LOGIC;
+    signal ARREADY_t           : STD_LOGIC;
+    signal RVALID_t            : STD_LOGIC;
+    -- internal registers
+    signal int_ap_idle         : STD_LOGIC;
+    signal int_ap_ready        : STD_LOGIC;
+    signal int_ap_done         : STD_LOGIC := '0';
+    signal int_ap_start        : STD_LOGIC := '0';
+    signal int_auto_restart    : STD_LOGIC := '0';
+    signal int_gie             : STD_LOGIC := '0';
+    signal int_ier             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_isr             : UNSIGNED(1 downto 0) := (others => '0');
+    signal int_in1             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_in2             : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_out_r           : UNSIGNED(31 downto 0) := (others => '0');
+    signal int_dim             : UNSIGNED(31 downto 0) := (others => '0');
+
+
+begin
+-- ----------------------- Instantiation------------------
+
+-- ----------------------- AXI WRITE ---------------------
+    AWREADY_t <=  '1' when wstate = wridle else '0';
+    AWREADY   <=  AWREADY_t;
+    WREADY_t  <=  '1' when wstate = wrdata else '0';
+    WREADY    <=  WREADY_t;
+    BRESP     <=  "00";  -- OKAY
+    BVALID    <=  '1' when wstate = wrresp else '0';
+    wmask     <=  (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
+    aw_hs     <=  AWVALID and AWREADY_t;
+    w_hs      <=  WVALID and WREADY_t;
+
+    -- write FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                wstate <= wrreset;
+            elsif (ACLK_EN = '1') then
+                wstate <= wnext;
+            end if;
+        end if;
+    end process;
+
+    process (wstate, AWVALID, WVALID, BREADY)
+    begin
+        case (wstate) is
+        when wridle =>
+            if (AWVALID = '1') then
+                wnext <= wrdata;
+            else
+                wnext <= wridle;
+            end if;
+        when wrdata =>
+            if (WVALID = '1') then
+                wnext <= wrresp;
+            else
+                wnext <= wrdata;
+            end if;
+        when wrresp =>
+            if (BREADY = '1') then
+                wnext <= wridle;
+            else
+                wnext <= wrresp;
+            end if;
+        when others =>
+            wnext <= wridle;
+        end case;
+    end process;
+
+    waddr_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (aw_hs = '1') then
+                    waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- AXI READ ----------------------
+    ARREADY_t <= '1' when (rstate = rdidle) else '0';
+    ARREADY <= ARREADY_t;
+    RDATA   <= STD_LOGIC_VECTOR(rdata_data);
+    RRESP   <= "00";  -- OKAY
+    RVALID_t  <= '1' when (rstate = rddata) else '0';
+    RVALID    <= RVALID_t;
+    ar_hs   <= ARVALID and ARREADY_t;
+    raddr   <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
+
+    -- read FSM
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                rstate <= rdreset;
+            elsif (ACLK_EN = '1') then
+                rstate <= rnext;
+            end if;
+        end if;
+    end process;
+
+    process (rstate, ARVALID, RREADY, RVALID_t)
+    begin
+        case (rstate) is
+        when rdidle =>
+            if (ARVALID = '1') then
+                rnext <= rddata;
+            else
+                rnext <= rdidle;
+            end if;
+        when rddata =>
+            if (RREADY = '1' and RVALID_t = '1') then
+                rnext <= rdidle;
+            else
+                rnext <= rddata;
+            end if;
+        when others =>
+            rnext <= rdidle;
+        end case;
+    end process;
+
+    rdata_proc : process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (ar_hs = '1') then
+                    case (TO_INTEGER(raddr)) is
+                    when ADDR_AP_CTRL =>
+                        rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
+                    when ADDR_GIE =>
+                        rdata_data <= (0 => int_gie, others => '0');
+                    when ADDR_IER =>
+                        rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
+                    when ADDR_ISR =>
+                        rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
+                    when ADDR_IN1_DATA_0 =>
+                        rdata_data <= RESIZE(int_in1(31 downto 0), 32);
+                    when ADDR_IN2_DATA_0 =>
+                        rdata_data <= RESIZE(int_in2(31 downto 0), 32);
+                    when ADDR_OUT_R_DATA_0 =>
+                        rdata_data <= RESIZE(int_out_r(31 downto 0), 32);
+                    when ADDR_DIM_DATA_0 =>
+                        rdata_data <= RESIZE(int_dim(31 downto 0), 32);
+                    when others =>
+                        rdata_data <= (others => '0');
+                    end case;
+                end if;
+            end if;
+        end if;
+    end process;
+
+-- ----------------------- Register logic ----------------
+    interrupt            <= int_gie and (int_isr(0) or int_isr(1));
+    ap_start             <= int_ap_start;
+    in1                  <= STD_LOGIC_VECTOR(int_in1);
+    in2                  <= STD_LOGIC_VECTOR(int_in2);
+    out_r                <= STD_LOGIC_VECTOR(int_out_r);
+    dim                  <= STD_LOGIC_VECTOR(int_dim);
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_start <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
+                    int_ap_start <= '1';
+                elsif (ap_ready = '1') then
+                    int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_done <= '0';
+            elsif (ACLK_EN = '1') then
+                if (ap_done = '1') then
+                    int_ap_done <= '1';
+                elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
+                    int_ap_done <= '0'; -- clear on read
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_idle <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_idle <= ap_idle;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ap_ready <= '0';
+            elsif (ACLK_EN = '1') then
+                if (true) then
+                    int_ap_ready <= ap_ready;
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_auto_restart <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
+                    int_auto_restart <= WDATA(7);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_gie <= '0';
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
+                    int_gie <= WDATA(0);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_ier <= "00";
+            elsif (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
+                    int_ier <= UNSIGNED(WDATA(1 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(0) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(0) = '1' and ap_done = '1') then
+                    int_isr(0) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ARESET = '1') then
+                int_isr(1) <= '0';
+            elsif (ACLK_EN = '1') then
+                if (int_ier(1) = '1' and ap_ready = '1') then
+                    int_isr(1) <= '1';
+                elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
+                    int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN1_DATA_0) then
+                    int_in1(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in1(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_IN2_DATA_0) then
+                    int_in2(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in2(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_OUT_R_DATA_0) then
+                    int_out_r(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_r(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+    process (ACLK)
+    begin
+        if (ACLK'event and ACLK = '1') then
+            if (ACLK_EN = '1') then
+                if (w_hs = '1' and waddr = ADDR_DIM_DATA_0) then
+                    int_dim(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_dim(31 downto 0));
+                end if;
+            end if;
+        end if;
+    end process;
+
+
+-- ----------------------- Memory logic ------------------
+
+end architecture behave;

hls/lab2/exported_ips/xilinx_com_hls_exercise_4/xgui/mmult_v3_0.tcl

@@ -0,0 +1,529 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+  ipgui::add_param $IPINST -name "Component_Name"
+  #Adding Page
+  set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+  #Adding Group
+  set group_0 [ipgui::add_group $IPINST -name "group 0" -parent ${Page_0} -display_name {m axi dev reg (AXI4 Master Interface)}]
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN1_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_IN2_MEM_CACHE_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_ID_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ID_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_DATA_WIDTH" -parent ${group_0} -widget comboBox
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ENABLE_USER_PORTS" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_AWUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_WUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_BUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_ARUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_RUSER_WIDTH" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_USER_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_PROT_VALUE" -parent ${group_0}
+  ipgui::add_param $IPINST -name "C_M_AXI_OUT_MEM_CACHE_VALUE" -parent ${group_0}
+
+
+
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN1_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN1_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN1_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN1_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_IN2_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_IN2_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_IN2_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_IN2_MEM_CACHE_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_ID_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_ID_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_ID_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ID_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ID_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_DATA_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ENABLE_USER_PORTS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS { PARAM_VALUE.C_M_AXI_OUT_MEM_ENABLE_USER_PORTS } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ENABLE_USER_PORTS
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_AWUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_AWUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_WUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_WUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_BUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_BUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_ARUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_ARUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to update C_M_AXI_OUT_MEM_RUSER_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_RUSER_WIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_USER_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_USER_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_PROT_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_PROT_VALUE
+	return true
+}
+
+proc update_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to update C_M_AXI_OUT_MEM_CACHE_VALUE when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to validate C_M_AXI_OUT_MEM_CACHE_VALUE
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	# WARNING: There is no corresponding user parameter named "C_S_AXI_PARAMS_ADDR_WIDTH". Setting updated value from the model parameter.
+set_property value 6 ${MODELPARAM_VALUE.C_S_AXI_PARAMS_ADDR_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN1_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_IN2_MEM_CACHE_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ID_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_AWUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_ARUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_WUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_RUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_BUSER_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_USER_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_PROT_VALUE}
+}
+
+proc update_MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE { MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}] ${MODELPARAM_VALUE.C_M_AXI_OUT_MEM_CACHE_VALUE}
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/constraints/mmult_ooc.xdc

@@ -0,0 +1,6 @@
+# This constraints file contains default clock frequencies to be used during out-of-context flows such as
+# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
+# to match the target frequencies. 
+# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
+create_clock -name ap_clk -period 10.000 [get_ports ap_clk]
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/doc/ReleaseNotes.txt

@@ -0,0 +1,10 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+
+Family       : zynquplus
+Device       : xczu3eg
+Package      : -sbva484
+Speed Grade  : -1-e
+Clock Period : 10.000 ns

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.mdd

@@ -0,0 +1,16 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+OPTION psf_version = 2.1;
+
+BEGIN driver mmult
+
+ OPTION supported_peripherals = (mmult_v4_0 );
+ OPTION driver_state = ACTIVE;
+ OPTION copyfiles = all;
+ OPTION name = mmult;
+ OPTION version = 4.0;
+
+END driver
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/data/mmult.tcl

@@ -0,0 +1,21 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+proc generate {drv_handle} {
+    xdefine_include_file $drv_handle "xparameters.h" "XMmult" \
+        "NUM_INSTANCES" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+
+    xdefine_config_file $drv_handle "xmmult_g.c" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR"
+
+    xdefine_canonical_xpars $drv_handle "xparameters.h" "XMmult" \
+        "DEVICE_ID" \
+        "C_S_AXI_PARAMS_BASEADDR" \
+        "C_S_AXI_PARAMS_HIGHADDR"
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/Makefile

@@ -0,0 +1,32 @@
+# ==============================================================
+# Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+# Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+# ==============================================================
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o 
+
+
+libs:
+	echo "Compiling mmult"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} $(OUTS)
+	make clean
+
+include: 
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.c

@@ -0,0 +1,198 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/************************** Function Implementation *************************/
+#ifndef __linux__
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(ConfigPtr != NULL);
+
+    InstancePtr->Params_BaseAddress = ConfigPtr->Params_BaseAddress;
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+#endif
+
+void XMmult_Start(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL) & 0x80;
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, Data | 0x01);
+}
+
+u32 XMmult_IsDone(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 1) & 0x1;
+}
+
+u32 XMmult_IsIdle(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    return (Data >> 2) & 0x1;
+}
+
+u32 XMmult_IsReady(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL);
+    // check ap_start to see if the pcore is ready for next input
+    return !(Data & 0x1);
+}
+
+void XMmult_EnableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0x80);
+}
+
+void XMmult_DisableAutoRestart(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_AP_CTRL, 0);
+}
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA, Data);
+}
+
+u32 XMmult_Get_in1(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN1_DATA);
+    return Data;
+}
+
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA, Data);
+}
+
+u32 XMmult_Get_in2(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IN2_DATA);
+    return Data;
+}
+
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA, Data);
+}
+
+u32 XMmult_Get_out_r(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_OUT_R_DATA);
+    return Data;
+}
+
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA, Data);
+}
+
+u32 XMmult_Get_dim(XMmult *InstancePtr) {
+    u32 Data;
+
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Data = XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_DIM_DATA);
+    return Data;
+}
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 1);
+}
+
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_GIE, 0);
+}
+
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register | Mask);
+}
+
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask) {
+    u32 Register;
+
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    Register =  XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER, Register & (~Mask));
+}
+
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask) {
+    Xil_AssertVoid(InstancePtr != NULL);
+    Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    XMmult_WriteReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR, Mask);
+}
+
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_IER);
+}
+
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr) {
+    Xil_AssertNonvoid(InstancePtr != NULL);
+    Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    return XMmult_ReadReg(InstancePtr->Params_BaseAddress, XMMULT_PARAMS_ADDR_ISR);
+}
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult.h

@@ -0,0 +1,108 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef XMMULT_H
+#define XMMULT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#ifndef __linux__
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_io.h"
+#else
+#include <stdint.h>
+#include <assert.h>
+#include <dirent.h>
+#include <fcntl.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <stddef.h>
+#endif
+#include "xmmult_hw.h"
+
+/**************************** Type Definitions ******************************/
+#ifdef __linux__
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+#else
+typedef struct {
+    u16 DeviceId;
+    u32 Params_BaseAddress;
+} XMmult_Config;
+#endif
+
+typedef struct {
+    u32 Params_BaseAddress;
+    u32 IsReady;
+} XMmult;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#ifndef __linux__
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+#else
+#define XMmult_WriteReg(BaseAddress, RegOffset, Data) \
+    *(volatile u32*)((BaseAddress) + (RegOffset)) = (u32)(Data)
+#define XMmult_ReadReg(BaseAddress, RegOffset) \
+    *(volatile u32*)((BaseAddress) + (RegOffset))
+
+#define Xil_AssertVoid(expr)    assert(expr)
+#define Xil_AssertNonvoid(expr) assert(expr)
+
+#define XST_SUCCESS             0
+#define XST_DEVICE_NOT_FOUND    2
+#define XST_OPEN_DEVICE_FAILED  3
+#define XIL_COMPONENT_IS_READY  1
+#endif
+
+/************************** Function Prototypes *****************************/
+#ifndef __linux__
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId);
+XMmult_Config* XMmult_LookupConfig(u16 DeviceId);
+int XMmult_CfgInitialize(XMmult *InstancePtr, XMmult_Config *ConfigPtr);
+#else
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName);
+int XMmult_Release(XMmult *InstancePtr);
+#endif
+
+void XMmult_Start(XMmult *InstancePtr);
+u32 XMmult_IsDone(XMmult *InstancePtr);
+u32 XMmult_IsIdle(XMmult *InstancePtr);
+u32 XMmult_IsReady(XMmult *InstancePtr);
+void XMmult_EnableAutoRestart(XMmult *InstancePtr);
+void XMmult_DisableAutoRestart(XMmult *InstancePtr);
+
+void XMmult_Set_in1(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in1(XMmult *InstancePtr);
+void XMmult_Set_in2(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_in2(XMmult *InstancePtr);
+void XMmult_Set_out_r(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_out_r(XMmult *InstancePtr);
+void XMmult_Set_dim(XMmult *InstancePtr, u32 Data);
+u32 XMmult_Get_dim(XMmult *InstancePtr);
+
+void XMmult_InterruptGlobalEnable(XMmult *InstancePtr);
+void XMmult_InterruptGlobalDisable(XMmult *InstancePtr);
+void XMmult_InterruptEnable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptDisable(XMmult *InstancePtr, u32 Mask);
+void XMmult_InterruptClear(XMmult *InstancePtr, u32 Mask);
+u32 XMmult_InterruptGetEnabled(XMmult *InstancePtr);
+u32 XMmult_InterruptGetStatus(XMmult *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_hw.h

@@ -0,0 +1,50 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+// params
+// 0x00 : Control signals
+//        bit 0  - ap_start (Read/Write/COH)
+//        bit 1  - ap_done (Read/COR)
+//        bit 2  - ap_idle (Read)
+//        bit 3  - ap_ready (Read)
+//        bit 7  - auto_restart (Read/Write)
+//        others - reserved
+// 0x04 : Global Interrupt Enable Register
+//        bit 0  - Global Interrupt Enable (Read/Write)
+//        others - reserved
+// 0x08 : IP Interrupt Enable Register (Read/Write)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x0c : IP Interrupt Status Register (Read/TOW)
+//        bit 0  - Channel 0 (ap_done)
+//        bit 1  - Channel 1 (ap_ready)
+//        others - reserved
+// 0x10 : Data signal of in1
+//        bit 31~0 - in1[31:0] (Read/Write)
+// 0x14 : reserved
+// 0x18 : Data signal of in2
+//        bit 31~0 - in2[31:0] (Read/Write)
+// 0x1c : reserved
+// 0x20 : Data signal of out_r
+//        bit 31~0 - out_r[31:0] (Read/Write)
+// 0x24 : reserved
+// 0x28 : Data signal of dim
+//        bit 31~0 - dim[31:0] (Read/Write)
+// 0x2c : reserved
+// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
+
+#define XMMULT_PARAMS_ADDR_AP_CTRL    0x00
+#define XMMULT_PARAMS_ADDR_GIE        0x04
+#define XMMULT_PARAMS_ADDR_IER        0x08
+#define XMMULT_PARAMS_ADDR_ISR        0x0c
+#define XMMULT_PARAMS_ADDR_IN1_DATA   0x10
+#define XMMULT_PARAMS_BITS_IN1_DATA   32
+#define XMMULT_PARAMS_ADDR_IN2_DATA   0x18
+#define XMMULT_PARAMS_BITS_IN2_DATA   32
+#define XMMULT_PARAMS_ADDR_OUT_R_DATA 0x20
+#define XMMULT_PARAMS_BITS_OUT_R_DATA 32
+#define XMMULT_PARAMS_ADDR_DIM_DATA   0x28
+#define XMMULT_PARAMS_BITS_DIM_DATA   32
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_linux.c

@@ -0,0 +1,147 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifdef __linux__
+
+/***************************** Include Files *********************************/
+#include "xmmult.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define MAX_UIO_PATH_SIZE       256
+#define MAX_UIO_NAME_SIZE       64
+#define MAX_UIO_MAPS            5
+#define UIO_INVALID_ADDR        0
+
+/**************************** Type Definitions ******************************/
+typedef struct {
+    u32 addr;
+    u32 size;
+} XMmult_uio_map;
+
+typedef struct {
+    int  uio_fd;
+    int  uio_num;
+    char name[ MAX_UIO_NAME_SIZE ];
+    char version[ MAX_UIO_NAME_SIZE ];
+    XMmult_uio_map maps[ MAX_UIO_MAPS ];
+} XMmult_uio_info;
+
+/***************** Variable Definitions **************************************/
+static XMmult_uio_info uio_info;
+
+/************************** Function Implementation *************************/
+static int line_from_file(char* filename, char* linebuf) {
+    char* s;
+    int i;
+    FILE* fp = fopen(filename, "r");
+    if (!fp) return -1;
+    s = fgets(linebuf, MAX_UIO_NAME_SIZE, fp);
+    fclose(fp);
+    if (!s) return -2;
+    for (i=0; (*s)&&(i<MAX_UIO_NAME_SIZE); i++) {
+        if (*s == '\n') *s = 0;
+        s++;
+    }
+    return 0;
+}
+
+static int uio_info_read_name(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/name", info->uio_num);
+    return line_from_file(file, info->name);
+}
+
+static int uio_info_read_version(XMmult_uio_info* info) {
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/version", info->uio_num);
+    return line_from_file(file, info->version);
+}
+
+static int uio_info_read_map_addr(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    info->maps[n].addr = UIO_INVALID_ADDR;
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/addr", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].addr);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+static int uio_info_read_map_size(XMmult_uio_info* info, int n) {
+    int ret;
+    char file[ MAX_UIO_PATH_SIZE ];
+    sprintf(file, "/sys/class/uio/uio%d/maps/map%d/size", info->uio_num, n);
+    FILE* fp = fopen(file, "r");
+    if (!fp) return -1;
+    ret = fscanf(fp, "0x%x", &info->maps[n].size);
+    fclose(fp);
+    if (ret < 0) return -2;
+    return 0;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, const char* InstanceName) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+	struct dirent **namelist;
+    int i, n;
+    char* s;
+    char file[ MAX_UIO_PATH_SIZE ];
+    char name[ MAX_UIO_NAME_SIZE ];
+    int flag = 0;
+
+    assert(InstancePtr != NULL);
+
+    n = scandir("/sys/class/uio", &namelist, 0, alphasort);
+    if (n < 0)  return XST_DEVICE_NOT_FOUND;
+    for (i = 0;  i < n; i++) {
+    	strcpy(file, "/sys/class/uio/");
+    	strcat(file, namelist[i]->d_name);
+    	strcat(file, "/name");
+        if ((line_from_file(file, name) == 0) && (strcmp(name, InstanceName) == 0)) {
+            flag = 1;
+            s = namelist[i]->d_name;
+            s += 3; // "uio"
+            InfoPtr->uio_num = atoi(s);
+            break;
+        }
+    }
+    if (flag == 0)  return XST_DEVICE_NOT_FOUND;
+
+    uio_info_read_name(InfoPtr);
+    uio_info_read_version(InfoPtr);
+    for (n = 0; n < MAX_UIO_MAPS; ++n) {
+        uio_info_read_map_addr(InfoPtr, n);
+        uio_info_read_map_size(InfoPtr, n);
+    }
+
+    sprintf(file, "/dev/uio%d", InfoPtr->uio_num);
+    if ((InfoPtr->uio_fd = open(file, O_RDWR)) < 0) {
+        return XST_OPEN_DEVICE_FAILED;
+    }
+
+    // NOTE: slave interface 'Params' should be mapped to uioX/map0
+    InstancePtr->Params_BaseAddress = (u32)mmap(NULL, InfoPtr->maps[0].size, PROT_READ|PROT_WRITE, MAP_SHARED, InfoPtr->uio_fd, 0 * getpagesize());
+    assert(InstancePtr->Params_BaseAddress);
+
+    InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+    return XST_SUCCESS;
+}
+
+int XMmult_Release(XMmult *InstancePtr) {
+	XMmult_uio_info *InfoPtr = &uio_info;
+
+    assert(InstancePtr != NULL);
+    assert(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+    munmap((void*)InstancePtr->Params_BaseAddress, InfoPtr->maps[0].size);
+
+    close(InfoPtr->uio_fd);
+
+    return XST_SUCCESS;
+}
+
+#endif

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/drivers/mmult_v4_0/src/xmmult_sinit.c

@@ -0,0 +1,43 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+#ifndef __linux__
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xmmult.h"
+
+extern XMmult_Config XMmult_ConfigTable[];
+
+XMmult_Config *XMmult_LookupConfig(u16 DeviceId) {
+	XMmult_Config *ConfigPtr = NULL;
+
+	int Index;
+
+	for (Index = 0; Index < XPAR_XMMULT_NUM_INSTANCES; Index++) {
+		if (XMmult_ConfigTable[Index].DeviceId == DeviceId) {
+			ConfigPtr = &XMmult_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return ConfigPtr;
+}
+
+int XMmult_Initialize(XMmult *InstancePtr, u16 DeviceId) {
+	XMmult_Config *ConfigPtr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	ConfigPtr = XMmult_LookupConfig(DeviceId);
+	if (ConfigPtr == NULL) {
+		InstancePtr->IsReady = 0;
+		return (XST_DEVICE_NOT_FOUND);
+	}
+
+	return XMmult_CfgInitialize(InstancePtr, ConfigPtr);
+}
+
+#endif
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_in1_loc.v

@@ -0,0 +1,88 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_in1_loc_ram (addr0, ce0, d0, we0, q0, addr1, ce1, q1,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input[AWIDTH-1:0] addr1;
+input ce1;
+output reg[DWIDTH-1:0] q1;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+always @(posedge clk)  
+begin 
+    if (ce1) begin
+        q1 <= ram[addr1];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_in1_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0,
+    address1,
+    ce1,
+    q1);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+input[AddressWidth - 1:0] address1;
+input ce1;
+output[DataWidth - 1:0] q1;
+
+
+
+mmult_in1_loc_ram mmult_in1_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ),
+    .addr1( address1 ),
+    .ce1( ce1 ),
+    .q1( q1 ));
+
+endmodule
+

hls/lab2/exported_ips/xilinx_com_hls_exercise_5/hdl/verilog/mmult_out_loc.v

@@ -0,0 +1,68 @@
+// ==============================================================
+// Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC v2020.1 (64-bit)
+// Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
+// ==============================================================
+`timescale 1 ns / 1 ps
+module mmult_out_loc_ram (addr0, ce0, d0, we0, q0,  clk);
+
+parameter DWIDTH = 32;
+parameter AWIDTH = 12;
+parameter MEM_SIZE = 4096;
+
+input[AWIDTH-1:0] addr0;
+input ce0;
+input[DWIDTH-1:0] d0;
+input we0;
+output reg[DWIDTH-1:0] q0;
+input clk;
+
+(* ram_style = "block" *)reg [DWIDTH-1:0] ram[0:MEM_SIZE-1];
+
+
+
+
+always @(posedge clk)  
+begin 
+    if (ce0) begin
+        if (we0) 
+            ram[addr0] <= d0; 
+        q0 <= ram[addr0];
+    end
+end
+
+
+endmodule
+
+`timescale 1 ns / 1 ps
+module mmult_out_loc(
+    reset,
+    clk,
+    address0,
+    ce0,
+    we0,
+    d0,
+    q0);
+
+parameter DataWidth = 32'd32;
+parameter AddressRange = 32'd4096;
+parameter AddressWidth = 32'd12;
+input reset;
+input clk;
+input[AddressWidth - 1:0] address0;
+input ce0;
+input we0;
+input[DataWidth - 1:0] d0;
+output[DataWidth - 1:0] q0;
+
+
+
+mmult_out_loc_ram mmult_out_loc_ram_U(
+    .clk( clk ),
+    .addr0( address0 ),
+    .ce0( ce0 ),
+    .we0( we0 ),
+    .d0( d0 ),
+    .q0( q0 ));
+
+endmodule
+